1. Stratix III Device Family Overview
SIII51001-1.8
The Stratix III family provides one of the most architecturally advanced,
high-performance, low-power FPGAs in the marketplace.
Stratix III FPGAs lower power consumption through Alteras innovative
Programmable Power Technology, which provides the ability to turn on the
performance where needed and turn down the power consumption for blocks not in
use. Selectable Core Voltage and the latest in silicon process optimizations are also
employed to deliver the industrys lowest power, high-performance FPGAs.
Specifically designed for ease of use and rapid system integration, the Stratix III
FPGA family offers two variants optimized to meet different application needs:
The Stratix III L family provides balanced logic, memory, and multiplier ratios for
mainstream applications.
The Stratix III E family is memory- and multiplier-rich for data-centric
applications.
Modular I/O banks with a common bank structure for vertical migration lend
efficiency and flexibility to the high-speed I/O. Package and die enhancements with
dynamic on-chip termination, output delay, and current strength control provide
best-in-class signal integrity.
Based on a 1.1-V, 65-nm all-layer copper SRAM process, the Stratix III family is a
programmable alternative to custom ASICs and programmable processors for
high-performance logic, digital signal processing (DSP), and embedded designs.
Stratix III devices include optional configuration bit stream security through volatile
or non-volatile 256-bit Advanced Encryption Standard (AES) encryption. Where
ultra-high reliability is required, Stratix III devices include automatic error detection
circuitry to detect data corruption by soft errors in the configuration random-access
memory (CRAM) and user memory cells.
Features Summary
Stratix III devices offer the following features:
48,000 to 338,000 equivalent logic elements (LEs) ( refer to Table 11)
2,430 to 20,497 Kbits of enhanced TriMatrix memory consisting of three RAM
block sizes to implement true dual-port memory and FIFO buffers
High-speed DSP blocks provide dedicated implementation of 99, 1212, 1818,
and 3636 multipliers (at up to 550 MHz), multiply-accumulate functions, and
finite impulse response (FIR) filters
I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling for
robust signal integrity
Programmable Power Technology, which minimizes power while maximizing
device performance
March 2010 Altera Corporation Stratix III Device Handbook, Volume 112 Chapter 1: Stratix III Device Family Overview
Features Summary
Selectable Core Voltage, available in low-voltage devices (L ordering code suffix),
enables selection of lowest power or highest performance operation
Up to 16 global clocks, 88 regional clocks, and 116 peripheral clocks per device
Up to 12 phase-locked loops (PLLs) per device that support PLL reconfiguration,
clock switchover, programmable bandwidth, clock synthesis, and dynamic phase
shifting
Memory interface support with dedicated DQS logic on all I/O banks
Support for high-speed external memory interfaces including DDR, DDR2,
DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular
I/O banks
Up to 1,104 user I/O pins arranged in 24 modular I/O banks that support a wide
range of industry I/O standards
Dynamic On-Chip Termination (OCT) with auto calibration support on all I/O
banks
High-speed differential I/O support with serializer/deserializer (SERDES) and
dynamic phase alignment (DPA) circuitry for 1.6 Gbps performance
Support for high-speed networking and communications bus standards including
SPI-4.2, SFI-4, SGMII, Utopia IV, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSI
The only high-density, high-performance FPGA with support for 256-bit AES
volatile and non-volatile security key to protect designs
Robust on-chip hot socketing and power sequencing support
Integrated cyclical redundancy check (CRC) for configuration memory error
detection with critical error determination for high availability systems support
Built-in error correction coding (ECC) circuitry to detect and correct data errors in
M144K TriMatrix memory blocks
Nios II embedded processor support
Support for multiple intellectual property megafunctions from Altera MegaCore
SM
functions and Altera Megafunction Partners Program (AMPP )
Stratix III Device Handbook, Volume 1 March 2010 Altera Corporation