FLEX 8000
FLEX 8000
Programmable Logic
Device Family
January 2003, ver. 11.1 Data Sheet
1
Low-cost, high-density, register-rich CMOS programmable logic
Features...
device (PLD) family (see Table 1)
2,500 to 16,000 usable gates
282 to 1,500 registers
System-level features
In-circuit reconfigurability (ICR) via external configuration
devices or intelligent controller
Fully compliant with the peripheral component interconnect
Special Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 5.0-V operation
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST)
circuitry compliant with IEEE Std. 1149.1-1990 on selected devices
TM
MultiVolt I/O interface enabling device core to run at 5.0 V,
3
while I/O pins are compatible with 5.0-V and 3.3-V logic levels
Low power consumption (typical specification is 0.5 mA or less in
standby mode)
Flexible interconnect
FastTrack Interconnect continuous routing structure for fast,
predictable interconnect delays
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
Dedicated cascade chain that implements high-speed, high-fan-in
logic functions (automatically used by software tools and
megafunctions)
Tri-state emulation that implements internal tri-state nets
Powerful I/O pins
Programmable output slew-rate control reduces switching noise
Table 1. FLEX 8000 Device Features
Feature EPF8282A EPF8452A EPF8636A EPF8820A EPF81188A EPF81500A
EPF8282AV
Usable gates 2,500 4,000 6,000 8,000 12,000 16,000
Flipflops 282 452 636 820 1,188 1,500
Logic array blocks (LABs) 26 42 63 84 126 162
Logic elements (LEs) 208 336 504 672 1,008 1,296
Maximum user I/O pins 78 120 136 152 184 208
Altera Corporation 1
DS-F8000-11.1FLEX 8000 Programmable Logic Device Family Data Sheet
JTAG BST circuitry Yes No Yes Yes No Yes
Peripheral register for fast setup and clock-to-output delay
...and More
Fabricated on an advanced SRAM process
Features
Available in a variety of packages with 84 to 304 pins (see Table 2)
Software design support and automatic place-and-route provided by
the Altera MAX+PLUS II development system for Windows-based
PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM
RISC System/6000 workstations
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, Synplicity, and Veribest
Table 2. FLEX 8000 Package Options & I/O Pin Count Note (1)
Device 84- 100- 144- 160- 160- 192- 208- 225- 232- 240- 280- 304-
Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin
PLCC TQFP TQFP PQFP PGA PGA PQFP BGA PGA PQFP PGA RQFP
EPF8282A 68 78
EPF8282AV 78
EPF8452A 68 68 120 120
EPF8636A 68 118 136 136
EPF8820A 112 120 152 152 152
EPF81188A 148 184 184
EPF81500A 181 208 208
Note:
(1) FLEX 8000 device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack (TQFP), plastic quad
flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), and pin-grid array (PGA) packages.
Alteras Flexible Logic Element MatriX (FLEX ) family combines the
General
benefits of both erasable programmable logic devices (EPLDs) and field-
Description
programmable gate arrays (FPGAs). The FLEX 8000 device family is ideal
for a variety of applications because it combines the fine-grained
architecture and high register count characteristics of FPGAs with the
high speed and predictable interconnect delays of EPLDs. Logic is
implemented in LEs that include compact 4-input look-up tables (LUTs)
and programmable registers. High performance is provided by a fast,
continuous network of routing resources.
2 Altera Corporation