MAX 3000A Programmable Logic Device Family June 2006, ver. 3.5 Data Sheet Highperformance, lowcost CMOS EEPROMbased programmable Features... logic devices (PLDs) built on a MAX architecture (see Table 1) 3.3-V in-system programmability (ISP) through the builtin IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability ISP circuitry compliant with IEEE Std. 1532 Builtin boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 Enhanced ISP features: Enhanced ISP algorithm for faster programming ISP Done bit to ensure complete programming Pull-up resistor on I/O pins during insystem programming Highdensity PLDs ranging from 600 to 10,000 usable gates 4.5ns pintopin logic delays with counter frequencies of up to 227.3 MHz TM MultiVolt I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0V, 3.3V, and 2.5V logic levels Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic Jlead chip carrier TM (PLCC), and FineLine BGA packages Hotsocketing support Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance Industrial temperature range Table 1. MAX 3000A Device Features Feature EPM3032A EPM3064A EPM3128A EPM3256A EPM3512A Usable gates 600 1,250 2,500 5,000 10,000 Macrocells 32 64 128 256 512 Logic array blocks 2 4 8 16 32 Maximum user I/O 34 66 98 161 208 pins t (ns) 4.5 4.5 5.0 7.5 7.5 PD t (ns) 2.9 2.8 3.3 5.2 5.6 SU t (ns) 3.0 3.1 3.4 4.8 4.7 CO1 f (MHz) 227.3 222.2 192.3 126.6 116.3 CNT Altera Corporation 1 DS-MAX3000A-3.5MAX 3000A Programmable Logic Device Family Data Sheet PCI compatible ...and More Busfriendly architecture including programmable slewrate control Features Opendrain output option Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls Programmable powersaving mode for a power reduction of over 50% in each macrocell Configurable expander productterm distribution, allowing up to 32 product terms per macrocell Programmable security bit for protection of proprietary designs Enhanced architectural features, including: 6 or 10 pin or logicdriven output enable signals Two global clock signals with optional inversion Enhanced interconnect resources for improved routability Programmable output slewrate control Software design support and automatic placeandroute provided by Alteras development systems for Windowsbased PCs and Sun SPARCstations, and HP 9000 Series 700/800 workstations Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from thirdparty manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest Programming support with the Altera master programming unit TM TM (MPU), MasterBlaster communications cable, ByteBlasterMV TM parallel port download cable, BitBlaster serial download cable as well as programming hardware from thirdparty manufacturers and TM any incircuit tester that supports Jam Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), or Serial Vector Format Files (.svf) MAX 3000A devices are lowcost, highperformance devices based on the General Altera MAX architecture. Fabricated with advanced CMOS technology, Description the EEPROMbased MAX 3000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices in the 4, 5, 6, 7, and 10 speed grades are compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2. 2 Altera Corporation