Enpirion Power Datasheet EV1340QI 5A PowerSoC Synchronous Highly Integrated DC-DC TM DDR2/3/4/QDR Memory Termination And Low VIN Operation Description Features The EV1340 is a Power System on a Chip High Efficiency, Up to 91% (PowerSoC) DC to DC converter in a 54 pin QFN Output Voltage Can Track VDDQ to within that is optimized for DDR2, DDR3, DDR4 and +/- 1.5% TM QDR VTT applications. It requires a nominal Source and Sink Capability up to 5A 3.3V power supply (AVIN) for the controller, and 2 125mm Total Solution Size an input supply (VDDQ) voltage range of 1.0V to VDDQ Range (1.0V to 1.8V ) 1.8V. It provides a tightly regulated and very stable output voltage (VTT) which tracks VDDQ Monotonic Startup With Pre-bias while sinking and sourcing up to 5A of output Programmable Soft-Start Time current. In addition, the EV1340 is an excellent Thermal Shutdown Protection solution for general low V applications where IN Over Current and Short Circuit Protection high efficiency is critical. Under-Voltage Protection The EV1340 utilizes innovative circuit RoHS Compliant, MSL level 3, 260C reflow techniques, high-density circuit integrations and optimized switching frequency along with Altera Enpirions proprietary inductor technology to Applications deliver high-quality, ultra compact, non-isolated Bus Termination: DDR2, DDR3, DDR4 & DC-DC conversion. QDR Memory The complete power converter solution enhances General Low V Applications IN productivity by offering greatly simplified board design, layout and manufacturing requirements. SCHOTTKY V CNTRL V V DDQ TT SW VDDQ VOUT R 1 R C EV1340 A IN C OUT1,2 RC ENABLE C A AVIN VFB PGND PGND VREF R AGND FQADJ D C C1 SS R B R C AVIN FS Figure 2: Typical V Application Schematic (V is TT DDQ the memory core voltage V is memory TT termination voltage that tracks V ) DDQ 2 Figure 1: EV1340 Total Solution Size ~ 125mm (not to scale) www.altera.com/enpirion 06218 March 24, 2015 Rev C EV1340QI Ordering Information Pin Assignments (Top View) Temp Rating Part Number (C) Package EV1340QI -40 to +85 54-pin QFN T&R EVB-EV1340QI QFN Evaluation Board Figure 3: Pinout Diagram (Top View). All pins must be soldered to PCB NOTE: There are specific keep-out areas underneath the EV1340 to consider when laying out a PCB for this device. Please see Figures 8, 10, and 11 for more layout details. Pin Description PIN NAME FUNCTION 1-9, 18, NO CONNECT: These pins must be soldered to PCB but not electrically connected to each 36, 37, 53, NC other or to any external signal, voltage, or ground. These pins may be connected internally. 54 Failure to follow this guideline may result in device damage. Regulated converter output. Decouple with output filter capacitor to PGND. Refer to layout 10 -17 VOUT section for specific layout requirements These pins are internally connected to the common switching node of the internal MOSFETs. 19, 20, SW The anode of a Schottky diode needs to be connected to these pins. The cathode of the diode needs to be connected to VDDQ. 21-27 PGND Input and output power ground. Refer to layout section for specific layout requirements. In DDR applications the input to this pin is the DDR core voltage. This is the input power supply to the power train which will be divided by two to create an output voltage that tracks 28-31 VDDQ with the input voltage applied to this pin. Decouple with input capacitor to PGND. Refer to layout section for specific layout requirements 32 AGND2 Ground for the gate driver supply. Connect to the GND plane with a via next to the pin. AVIN1, Analog input voltage for the controller circuits. Each of these pins needs to be separately 33, 39 AVIN2 connected to the 3.3V input supply. Decouple with a capacitor to AGND. Internal regulated voltage used for the internal control circuitry. This pin is reserved for Altera 34 VDDB Enpirion testing, and should be left floating. 35 BGND This pin is reserved for Altera Enpirion testing, and should be left floating. This is the Device Enable pin. Floating this pin or a high level enables the device while a low 38 ENABLE level disables the device. 40 AGND This is the quiet ground for the controller. Connect to the GND plane with a via next to the pin. POK is a logical AND of VDDQOK and the internally generated POK of the EV1340. POK is an open drain logic output that requires an external pull-up resistor. This pin guarantees a 41 POK logic low even when the EV1340 is completely un-powered. This pin can sink a maximum 4mA. The pull-up resistor may be connected to a power supply other than AVIN or VDDQ but the voltage should be <3.6Volts. This is the feedback input pin which is always active. A resistor divider connects from the output to AGND. The mid-point of the resistor divider is connected to VFB. (A feed-forward 42 VFB capacitor and a resistor are required across the upper resistor.) The output voltage regulates so as to make the VFB node voltage = 600mV. 2 www.altera.com/enpirion 06218 March 24, 2015 Rev C