Enpirion Power Evaluation Board User Guide EN5364QI PowerSoC Enpirion EN5364QI 6A DCDC Converter w/Integrated Inductor Evaluation Board Introduction Thank you for choosing Altera Enpirion power products This user guide should be used together with the latest device datasheet. The EN5364QI features integrated inductor, power MOSFETS, Controller, bulk of the compensation Network, and protection circuitry against system faults. This level of integration delivers a substantial reduction in footprint and part count over competing solutions. However, the evaluation board is not optimized for minimum footprint rather for engineering ease of evaluation through programming options, clip leads, test points etc. The EN5364QI device is feature rich and supports the following additional functions: o Margining The output voltage can be changed by 2.5%, 5% or 10% about the nominal, under digital control using ternary pins MAR 1:2 Margining is highly valued for system robustness verification and reliability studies. Note: POK automatically scales with margining. o Phase Lock - The internal switching frequency can be phase locked to an external clock source (or another EN5364QI) by connecting such a clock source to pin S IN. This feature is highly valued to keep beat frequencies (between a system sampling clock and the DC/DC converter switching frequency) out of the desired signal band. o Delay - A delayed version of the internal switching clock (or the PWM signal) is available at pin S OUT. This may be input to another EN5364QI device. o The delay is programmable by means of a single resistor connected between pin S delay and AGND. This feature allows the control of input ripple when multiple EN5364QI devices are used on a system board. o Pre-bias operation When the device pre-bias is enabled (jumper provided), the device will monotonically ramp-up its output voltage from a pre-bias voltage level to the programmed output voltage level under control of Enable signal. The pre-bias (Back-feed) voltage may be coupled to the output via a diode. This diode (D2) is populated on the board. Back-feed voltage may be applied at BF IN (TP18) Page 1 of 11 www.altera.com/enpirion Enpirion Power Evaluation Board User Guide EN5364QI PowerSoC o Parallel Mode operation Up to 4 EN5364QI devices may be operated in parallel when load currents greater than 6A is desired. In parallel mode, one device is designated the Master and up to 3 devices operate in slave mode, controlled by the Master. The PWM output of the Master is routed to slave devices. By daisy chaining the Slave devices even more devices can be operated in parallel but practical considerations, such as board layout would limit the number of slave devices to three. o Soft-Start A 15nF (C11) soft-start capacitor is populated on the evaluation board for an output voltage ramp time of ~1ms. This may be swapped for a different value capacitor if a different ramp time is desired. To limit the inrush current this capacitor value should be greater than 4.7nF. The output voltage rise time is ~65k*C . SS The EN5364QI features a customer programmable output voltage by means of a resistor divider. The resistor divider allows the user to set the V to any value within the range 0.6V to approximately (V -0.5V). OUT IN Referring to Figure 1, the evaluation board, as shipped is populated with a single R , a single C , and four possible R resistors. A jumper selects A A B one of the 4 R resistors to produce a voltage of 0.804, 0.998, 1.2 or B 1.8Volts. You can populate more than one R jumper position to get even B higher output voltages. See VOUT Programming section in the evaluation board schematic (Figure 7). The EN5364QI includes the bulk of the compensation network internally. However, an external phase-lead (zero) capacitor is required as part of the feedback. This network is shown in Figure -1. Appropriate component values allow for optimum compensation for a given Input voltage and choice of loop bandwidth. The equations in Figure 1 provide the details to calculate component values. MAR1 and MAR2 are ternary input signals. The pins are allowed to be in a low state (tied to GND), a high state (tied to V ), or a float state. Table-1 IN shows the margining truth table. Accordingly, the output voltage can be nominal or 2.5%, 5% or 10% about the nominal. 7 out of 9 possible states of MAR 1:2 are used for margining. The other two states are reserved for diagnostics. If tying MAR 1,2 to V , a series resistor is IN recommended to reduce the pin input current (see Figure 2). A footprint is provided for a SMC connector (not populated) for S IN. A clock source (3.6 to 4.4MHz) may be applied to S IN to synchronize the device switching frequency to the external source. S OUT will output a clock signal synchronous with the switching frequency, with a phase delay. S OUT of one EN5364QI may be connected to S IN of another EN5364QI device in different modes of operation. The phase delay is set by connecting a resistor from S delay to AGND. The delay is approximately: Delay (nsec) = 2* S delay resistance in k. Page 2 of 11 www.altera.com/enpirion