EVB-EV1320QI Intel

Enpirion Power Evaluation Board User Guide EV1320QI PowerSoC Enpirion EV1320QI 2A Sink/Source DDR Termination Converter Evaluation Board Introduction Thank you for choosing Altera Enpirion power products Along with this document you will also need the latest device datasheet. The EV1320QI operates by charging a pair of capacitors in series and connecting them in parallel to generate an output voltage which is nearly one half the input voltage. There is no feedback control, and the output voltage is not regulated. The output voltage is directly proportional to the input voltage and is also affected by the load. The division by two property makes the EV1320 a suitable part for VTT applications for up to 2A of load current. The capacitor configuration around the EV1320 package determines how the device operates. For this evaluation board, the capacitors around the device have been chosen to minimize the output voltage droop as a function of load current. Please see Figure 1. ENABLE ENABLE V TT VDDQ VOUT VDDQ 22uF + C1P 2 x 10uF (0603) 22uF + 22uF + 2 x 10uF 2 x 10uF PGND (0603) (0603) C1N POK POK PGND 100k 3.3V AVIN SS 15nF AGND Figure 1: EV1320 Simplified Application Schematic Page 1 of 6 Enpirion Power Evaluation Board User Guide EV1320QI PowerSoC Quick Start Guide Jumper VIN GND SIDE SIDE Figure 2: J2 allows control of the Enable pin. The jumper on Enable pin as shown in Figure 2 is in disable mode. When jumper is between the middle and right pins the signal pin is connected to ground or logic low. When the jumper is between the left and middle pins, the signal pin is connected to AVIN or logic High. WARNING: complete steps 1 through 4 before applying power to the EV1320QI evaluation board. STEP 1: Set the ENA jumper to the Disable Position. See Figure 2 above. STEP 2: With the AVIN power supply off, connect it to the input connectors AVIN (TP14) and PGND (TP16) as indicated in Figure 3 and set the power supply to the desired voltage (3.3V nominal). STEP 3: With the VDDQ power supply off, connect it to the input power connectors VDDQ (TP12) and PGND (TP17) as indicated in Figure 3, and set the power supply to the desired voltage (1.2V1.8V). CAUTION: Be mindful of the polarity and magnitude. This evaluation board has no reverse polarity or voltage clamping protection on it. STEP 4: Connect the load to the output connectors VOUT (TP13) and PGND (TP15), as indicated in Figure 3. STEP 5: Power up the board by turning on the AVIN power supply first and then the VDDQ supply. Next, move the ENA jumper to the enabled position. The EV1320QI is now powered up and VOUT should be half of VDDQ. You can now make Efficiency, Ripple, Line/Load Regulation, Load transient, Power OK, and temperature related measurements. STEP 6: Power Up/Down Behavior Remove ENA jumper and connect a pulse generator (output disabled) signal to the middle pin of ENA and Ground. Set the pulse amplitude to swing from 0 to 2.5 volts. Set the pulse period to 10msec, duty cycle to 50% and fast transition (<1usec.) Hook up oscilloscope probes to ENA, POK and V with clean ground OUT Page 2 of 6