TM Intel386 SX MICROPROCESSOR Y Y Full 32-Bit Internal Architecture Large Uniform Address Space 8-, 16-, 32-Bit Data Types 16 Megabyte Physical 8 General Purpose 32-Bit Registers 64 Terabyte Virtual 4 Gigabyte Maximum Segment Size TM Y Runs Intel386 Software in a Cost TM Y Effective 16-Bit Hardware Environment Numerics Support with the Intel387 Runs Same Applications and O.S. s SX Math CoProcessor TM as the Intel386 DX Processor Y On-Chip Debugging Support Including Object Code Compatible with 8086, Breakpoint Registers TM 80186, 80286, and Intel386 Y Complete System Development Processors Support Y High Performance 16-Bit Data Bus Software: C, PL/M, Assembler 16, 20, 25 and 33 MHz Clock Debuggers: PMON-386 DX, Two-Clock Bus Cycles TM ICE -386 SX Address Pipelining Allows Use of Y High Speed CHMOS IV Technology Slower/Cheaper Memories Y Operating Frequency: Y Integrated Memory Management Unit Standard Virtual Memory Support (Intel386 SX -33, -25, -20, -16) Optional On-Chip Paging Min/Max Frequency 4 Levels of Hardware Enforced (4/33, 4/25, 4/20, 4/16) MHz Protection Low Power MMU Fully Compatible with Those of (Intel386 SX -33, -25, -20, -16, -12) the 80286 and Intel386 DX CPUs Min/Max Frequency Y Virtual 8086 Mode Allows Execution of (2/33, 2/25, 2/20, 2/16, 2/12) MHz 8086 Software in a Protected and Y 100-Pin Plastic Quad Flatpack Package Paged System (See Packaging Outlines and Dimensions 231369) TM The Intel386 SX Microprocessor is an entry-level 32-bit CPU with a 16-bit external data bus and a 24-bit TM external address bus. The Intel386 SX CPU brings the vast software library of the Intel386 Architecture to entry-level systems. It provides the performance benefits of a 32-bit programming architecture with the cost savings associated with 16-bit hardware systems. 24018747 TM Intel386 SX Pipelined 32-Bit Microarchitecture *Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. COPYRIGHT INTEL CORPORATION, 1995 January 1994 Order Number: 240187-008TM Intel386 SX MICROPROCESSOR TM Intel386 SX MicroProcessor CONTENTS PAGE CONTENTS PAGE 1.0 PIN DESCRIPTION 3 5.0 FUNCTIONAL DATA 39 5.1 Signal Description Overview 39 2.0 BASE ARCHITECTURE 6 5.2 Bus Transfer Mechanism 45 2.1 Register Set 6 5.3 Memory and I/O Spaces 45 2.2 Instruction Set 10 5.4 Bus Functional Description 45 2.3 Memory Organization 11 5.5 Self-test Signature 63 2.4 Addressing Modes 12 5.6 Component and Revision 2.5 Data Types 15 Identifiers 63 2.6 I/O Space 15 5.7 Coprocessor Interfacing 63 2.7 Interrupts and Exceptions 17 6.0 PACKAGE THERMAL 2.8 Reset and Initialization 20 SPECIFICATIONS 64 2.9 Testability 20 7.0 ELECTRICAL SPECIFICATIONS 64 2.10 Debugging Support 21 7.1 Power and Grounding 64 3.0 REAL MODE ARCHITECTURE 22 7.2 Maximum Ratings 65 3.1 Memory Addressing 22 7.3 D.C. Specifications 66 3.2 Reserved Locations 23 7.4 A.C. Specifications 68 3.3 Interrupts 23 TM 7.5 Designing for ICE -Intel386 SX 3.4 Shutdown and Halt 23 Emulator 78 3.5 LOCK Operations 23 8.0 DIFFERENCES BETWEEN THE TM Intel386 SX CPU and the 4.0 PROTECTED MODE TM Intel386 DX CPU 79 ARCHITECTURE 24 4.1 Addressing Mechanism 24 9.0 INSTRUCTION SET 80 4.2 Segmentation 24 TM 9.1 Intel386 SX CPU Instruction Encoding and Clock Count Summary 80 4.3 Protection 29 9.2 Instruction Encoding 95 4.4 Paging 33 4.5 Virtual 8086 Environment 36 2