IS66WVD4M16ALL 64Mb Async and Burst CellularRAM 2.0 Overview The IS66WVD4M16ALL is an integrated memory device containing 64Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 4M words by 16 bits. The device uses a multiplexed address and data bus scheme to minimize pins and includes a industry standard burst mode for increased read and write bandwidth. The device includes several power saving modes : Reduced Array Refresh mode where data is retained in a portion of the array and Temperature Controlled Refresh. Both these modes reduce standby current drain. The device can be operated in a standard asynchronous mode and high performance burst mode. The die has separate power rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core. Features Single device supports asynchronous and burst Low Power Consumption operation Asynchronous Operation < 25 mA Mixed Mode supports asynchronous write and Burst operation < 35 mA ( 104Mhz) synchronous read operation Standby < 150 uA(max.) Dual voltage rails for optional performance Deep power-down (DPD) < 3uA (Typ) VDD 1.7V~1.95V, VDDQ 1.7V~1.95V Low Power Feature Multiplexed address and data bus Reduced Array Refresh ADQ0~ADQ15 Temperature Controlled Refresh Asynchronous mode read access : 70ns Operation Frequency up to 104MHz Burst mode for Read and Write operation Operating temperature Range 4, 8, 16 or Continuous Industrial -40C~85C Package: 54-ball VFBGA Copyright 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances 1 Rev.A June 2011 www.issi.com - SRAM issi.comIS66WVD4M16ALL General Description CellularRAM (Trademark of MicronTechnology) products are high-speed, CMOS pseudo-static random access memories developed for low-power, portable applications. The 64Mb DRAM core device is organized as 4 Meg x 16 bits. This device is a variation of the industry-standard Flash control interface, with a multiplexed address/data bus. The multiplexed address and data functionality dramatically reduce the required signal count, and increase READ/WRITE bandwidth. To operate seamlessly on a burst Flash bus, CellularRAM products have incorporated a transparent self-refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. Two user-accessible control registers define device operation. The bus configuration register (BCR) defines how the CellularRAM device interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. Special attention has been focused on standby current consumption during self refresh. CellularRAM products include three mechanisms to minimize standby current. Partial array refresh (PAR) enables the system to limit refresh to only that part of the DRAM array that contains essential data. Temperature-compensated refresh (TCR) uses an on-chip sensor to adjust the refresh rate to match the device temperature the refresh rate decreases at lower temperatures to minimize current consumption during standby. Deep power-down (DPD) enables the system to halt the refresh operation altogether when no vital information is stored in the device. The system-configurable refresh mechanisms are adjusted through the RCR. This CellularRAM device is compliant with the industry-standard CellularRAM 2.0 feature set established by the CellularRAM Workgroup. It includes support for both variable and fixed latency, with three drive strengths, a variety of wrap options, and a device ID register (DIDR). A16~A21 Address Decode Logic Input 4096K X 16 /Output Refresh Configuration Register DRAM Mux (RCR) Memory Array And Buffers Device ID Register (DIDR) Bus Configuration Register (BCR) CE WE OE CLK Control ADV Logic CRE LB ADQ0~ADQ15 UB WAIT Functional Block Diagram 2 Rev.A June 2011 www.issi.com - SRAM issi.com