Data Sheet: JN5148-001 Preliminary IEEE802.15.4 Wireless Microcontroller Features: Transceiver Overview 2.4GHz IEEE802.15.4 compliant The JN5148-001 is an ultra low power, high performance wireless Time of Flight ranging engine microcontroller targeted at ZigBee PRO networking applications. The device 128-bit AES security processor features an enhanced 32-bit RISC processor offering high coding efficiency MAC accelerator with packet through variable width instructions, a multi-stage instruction pipeline and low formatting, CRCs, address check, power operation with programmable clock speeds. It also includes a 2.4GHz auto-acks, timers IEEE802.15.4 compliant transceiver, 128kB of ROM, 128kB of RAM, and a rich mix of analogue and digital peripherals. The large memory footprint 500 & 667kbps data rate modes allows the device to run both a network stack, e.g. ZigBee PRO, and an Integrated sleep oscillator for low embedded application or in a co-processor mode. The operating current is power below 18mA, allowing operation direct from a coin cell. On chip power regulation for 2.0V Enhanced peripherals include low power pulse counters running in sleep to 3.6V battery operation mode designed for pulse counting in AMR applications and a unique Time Deep sleep current 100nA of Flight ranging engine, allowing accurate location services to be 2 Sleep current with active sleep implemented on wireless sensor networks. It also includes a 4-wire I S timer 1.25A audio interface, to interface directly to mainstream audio CODECs, as well as conventional MCU peripherals. < 0.50 external component cost Rx current 17.5mA Block Diagram Tx current 15.0mA Receiver sensitivity -95dBm Time of Flight RAM ROM SPI Engine 128kB 128kB Transmit power 2.5dBm 2-Wire Serial 2.4GHz O-QPSK Features: Microcontroller 32-bit Radio Timers Modem RISC CPU Low power 32-bit RISC CPU, 4 to UAR Ts 32MHz clock speed 32-byte 4-Wire Audio IEEE802.15.4 OTP eFuse Variable instruction width for high MAC Sleep Counters Watchdog Accelerator coding efficiency XTAL Timer 12-bit ADC, Comparators Multi-stage instruction pipeline 128-bit AES Power 12-bit DACs, Encryption Management 128kB ROM and 128kB RAM for Temp Sensor Accelerator bootloaded program code & data JTAG debug interface 4-input 12-bit ADC, 2 12-bit Benefits Applications DACs, 2 comparators Single chip integrates Robust and secure low power 3 application timer/counters, transceiver and wireless applications microcontroller for wireless 2 UARTs ZigBee PRO networks sensor networks SPI port with 5 selects Smart metering Large memory footprint to (e.g. AMR) 2-wire serial interface run ZigBee PRO together Home and commercial building 4-wire digital audio interface with an application automation Watchdog timer Very low current solution for Location Aware services e.g. long battery life Low power pulse counters Asset Tracking Highly featured 32-bit RISC Up to 21 DIO Industrial systems CPU for high performance Industrial temp (-40C to +85C) and low power Telemetry System BOM is low in Remote Control 8x8mm 56-lead Punched QFN component count and cost Toys and gaming peripherals Lead-free and RoHS compliant Extensive user peripherals Jennic 2009 JN-DS-JN5148-001 1v2 1 Preliminary Jennic Contents 1 Introduction 6 1.1 Wireless Transceiver 6 1.2 RISC CPU and Memory 6 1.3 Peripherals 7 1.4 Block Diagram 8 2 Pin Configurations 9 2.1 Pin Assignment 10 2.2 Pin Descriptions 12 2.2.1 Power Supplies 12 2.2.2 Reset 12 2.2.3 32MHz Oscillator 12 2.2.4 Radio 12 2.2.5 Analogue Peripherals 13 2.2.6 Digital Input/Output 13 3 CPU 15 4 Memory Organisation 16 4.1 ROM 16 4.2 RAM 17 4.3 OTP eFuse Memory 17 4.4 External Memory 17 4.4.1 External Memory Encryption 18 4.5 Peripherals 18 4.6 Unused Memory Addresses 18 5 System Clocks 19 5.1 16MHz System Clock 19 5.1.1 32MHz Oscillator 19 5.1.2 24MHz RC Oscillator 19 5.2 32kHz System Clock 20 5.2.1 32kHz RC Oscillator 20 5.2.2 32kHz Crystal Oscillator 20 5.2.3 32kHz External Clock 20 6 Reset 21 6.1 Internal Power-on Reset 21 6.2 External Reset 22 6.3 Software Reset 22 6.4 Brown-out Detect 23 6.5 Watchdog Timer 23 7 Interrupt System 24 7.1 System Calls 24 7.2 Processor Exceptions 24 7.2.1 Bus Error 24 7.2.2 Alignment 24 7.2.3 Illegal Instruction 24 7.2.4 Stack Overflow 24 7.3 Hardware Interrupts 25 2 JN-DS-JN5148-001 1v2 Jennic 2009 Preliminary