IECQ-CECC MLCC Capacitors MLCC High Reliability IECQ-CECC Ranges Electrical Details A range of specialist high reliability MLCCs for use in Capacitance Range 0.47pF to 6.8F critical or high reliability environments. All fully C0G/NP0 0 30ppm/C Temperature Coefficient of tested/approved and available with a range of suitable Capacitance (TCC) X7R 15% from -55C to +125C termination options, including tin/lead plating and Syfer FlexiCap. Cr > 50pF 0.0015 C0G/NP0 Dissipation Factor Cr 50pF = 0.0015(15Cr+0.7) X7R 0.025 Insulation Resistance (IR) 100G or 1000secs (whichever is the less) Voltage applied for 5 1 seconds, 50mA Dielectric Withstand Voltage (DWV) charging current maximum C0G/NP0 Zero Ageing Rate X7R <2% per time decade IECQ-CECC maximum capacitance values 0603 0805 1206 1210 1808 1812 2220 2225 C0G/NP0 1.5nF 6.8nF 22nF 33nF 33nF 100nF 150nF 220nF 16V X7R 100nF 330nF 1.0 F 1.5 F 1.5 F 3.3 F 5.6 F 6.8 F C0G/NP0 1.0nF 4.7nF 15nF 22nF 27nF 68nF 100nF 150nF 25V X7R 56nF 220nF 820nF 1.2 F 1.2 F 2.2 F 4.7 F 5.6 F C0G/NP0 470pF 2.7nF 10nF 18nF 18nF 33nF 68nF 100nF 50/63V X7R 47nF 220nF 470nF 1.0 F 680nF 1.5 F 2.2 F 3.3 F C0G/NP0 330pF 1.8nF 6.8nF 12nF 12nF 27nF 47nF 68nF 100V X7R 10nF 47nF 150nF 470nF 330nF 1.0 F 1.5 F 1.5 F C0G/NP0 100pF 680pF 2.2nF 4.7nF 4.7nF 12nF 22nF 27nF 200/250V X7R 5.6nF 27nF 100nF 220nF 180nF 470nF 1.0 F 1.0 F C0G/NP0 n/a 330pF 1.5nF 3.3nF 3.3nF 10nF 15nF 22nF 500V X7R n/a 8.2nF 33nF 100nF 100nF 270nF 560nF 820nF C0G/NP0 n/a n/a 470pF 1.0nF 1.2nF 3.3nF 8.2nF 10nF 1kV X7R n/a n/a 4.7nF 15nF 18nF 56nF 120nF 150nF Ordering Information IECQ-CECC Range 1210 Y 100 0103 J D T Capacitance in Pico Capacitance Dielectric Chip Size Termination Rated Voltage Packaging Suffix code farads (pF) Tolerance Codes 0603 Y = FlexiCap 016 = 16V First digit is 0. <10pF D = X7R (2R1) with T = 178mm Used for specific termination base with IECQCECC release (7) reel customer 0805 025 = 25V Second and third digits are B = 0.1pF nickel barrier (100% requirements significant figures of F = C0G/NP0 R = 330mm 1206 050 = 50V C = 0.25pF matte tin plating). capacitance code. The fourth (1B/NP0) with (13) reel 1210 063 = 63V D = 0.5pF RoHS compliant. digit is number of zeros IECQCECC release B = Bulk pack 1808 100 = 100V 10pF H = FlexiCap following. Example: B = 2X1/BX - tubs or trays 1812 termination base with 200 = 200V F = 1% 0103 = 10nF released in nickel barrier (Tin/ accordance with 2220 250 = 250V G = 2% lead plating with min. IECQ-CECC 2225 500 = 500V J = 5% 10% lead). Not RoHS R = 2C1/BZ 1K0 = 1kV K = 10% compliant. released in M = 20% F = Silver Palladium. accordance with RoHS compliant. IECQ-CECC J = Silver base with For B and R codes nickel barrier (100% please refer to matte tin plating). TCC/VCC range for RoHS compliant. full capacitance A = Silver base with values nickel barrier (Tin/lead plating with min. 10% lead). Not RoHS compliant. Knowles 2014 IECQ-CECCDatasheet Issue 4 (P109796) Release Date 04/11/14 Page 1 of 9 Tel: +44 1603 723300 Email SyferSales knowles.com www.knowlescapacitors.com/syfer Soldering Information Rework of Chip Capacitors Syfer MLCCs are compatible with all recognised Syfer recommend hot air/gas as the preferred method of soldering/mounting methods for chip capacitors. A detailed applying heat for rework. Apply even heat surrounding the application note is available at syfer.com component to minimise internal thermal gradients. Soldering irons or other techniques that apply direct heat to the chip or Reflow Soldering surrounding area should not be used as these can result in micro cracks being generated. Syfer recommend reflow soldering as the preferred method for mounting MLCCs. Syfer MLCCs can be reflow soldered using a Minimise the rework heat duration and allow components to reflow profile generally defined in IPC/FEDEC J-STD-020. Sn cool naturally after soldering. plated termination chip capacitors are compatible with both conventional and lead free soldering with peak temperatures of Use of Silver Loaded Epoxy Adhesives 260 to 270C acceptable. Chip capacitors can be mounted to circuit boards using silver The heating ramp rate should be such that components see a loaded adhesive provided the termination material of the temperature rise of 1.5 to 4C per second to maintain capacitor is selected to be compatible with the adhesive. This temperature uniformity through the MLCC. is normally PdAg. Standard tin finishes are often not recommended for use with silver loaded epoxies as there can The time for which the solder is molten should be maintained be electrical and mechanical issues with the joint integrity due at a minimum, so as to prevent solder leaching. Extended to material mismatch. times above 230C can cause problems with oxidation of Sn plating. Use of an inert atmosphere can help if this problem is encountered. Palladium/Silver (Pd/Ag) terminations can be Handling & Storage particularly susceptible to leaching with free lead, tin rich solders and trials are recommended for this combination. Components should never be handled with fingers perspiration and skin oils can inhibit solderability and will Cooling to ambient temperature should be allowed to occur aggravate cleaning. naturally, particularly if larger chip sizes are being soldered. Natural cooling allows a gradual relaxation of thermal Chip capacitors should never be handled with metallic mismatch stresses in the solder joints. Forced cooling should instruments. Metal tweezers should never be used as these be avoided as this can induce thermal breakage. can chip the product and leave abraded metal tracks on the product surface. Plastic or plastic coated metal types are Wave Soldering readily available and recommended these should be used Wave soldering is generally acceptable, but the thermal with an absolute minimum of applied pressure. stresses caused by the wave have been shown to lead to potential problems with larger or thicker chips. Particular care Incorrect storage can lead to problems for the user. Rapid should be taken when soldering SM chips larger than size 1210 tarnishing of the terminations, with an associated degradation and with a thickness greater than 1.0mm for this reason. of solderability, will occur if the product comes into contact with industrial gases such as sulphur dioxide and chlorine. Maximum permissible wave temperature is 270C for SM Storage in free air, particularly moist or polluted air, can result chips. in termination oxidation. The total immersion time in solder should be kept to a Packaging should not be opened until the MLCs are required minimum. It is strongly recommended that Sn/Ni plated for use. If opened, the pack should be re-sealed as soon as terminations are specified for wave soldering applications. practicable. Alternatively, the contents could be kept in a sealed container with an environmental control agent. Solder Leaching Long term storage conditions, ideally, should be temperature Leaching is the term for the dissolution of silver into the solder controlled between -5 and +40C and humidity controlled causing a failure of the termination system which causes between 40% and 60% R.H. increased ESR, tan and open circuit faults, including ultimately the possibility of the chip becoming detached. Taped product should be stored out of direct sunlight, which might promote deterioration in tape or adhesive performance. Leaching occurs more readily with higher temperature solders and solders with a high tin content. Pb free solders can be very Product, stored under the conditions recommended above, in prone to leaching certain termination systems. To prevent its as received packaging, has a minimum shelf life of 2 leaching, exercise care when choosing solder allows and years. minimize both maximum temperature and dwell time with the molten solder. SM Pad Design Plated terminations with nickel or copper anti-leaching barrier layers are available in a range of top coat finishes to prevent Syfer conventional 2-terminal chip capacitors can generally be TM leaching occurring. These finishes also include Syfer FlexiCap mounted using pad designs in accordance with IPC-7351, for improved stress resistance post soldering. Generic Requirements for Surface Mount Design and Land Pattern Standards, but there are some other factors that have Multilayer ceramic chip with nickel or copper barrier been shown to reduce mechanical stress, such as reducing the termi pad width to less than the chip width. In addition, the position natio of the chip on the board should also be considered. n 3-terminal components are not specifically covered by IPC- 7351, but recommended pad dimensions are included in the Syfer catalogue/website for these components. Knowles 2014 IECQ-CECCDatasheet Issue 4 (P109796) Release Date 04/11/14 Page 2 of 9 Tel: +44 1603 723300 Email SyferSales knowles.com www.knowlescapacitors.com/syfer