ispPAC-POWR6AT6-01SN32I Lattice

ispPAC-POWR6AT6 In-System Programmable Power Supply Monitoring and Margining Controller November 2013 Data Sheet DS1016 Application Block Diagram Features Vout Power Supply Margin and Trim Functions 3.3V Trim and margin up to six power supplies Trim 2 Dynamic voltage control through I C Vout Four hardware selectable voltage profiles 2.5V Trim Independent Digital Closed-Loop Trim function Vout for each output 1.8V Trim Analog Input Monitoring Vout Six analog monitor inputs POL 1 Differential input architecture for accurate Trim remote ground sensing Vout POL 2 10-bit ADC for direct voltage measurements Trim 2 2-Wire (I C/SMBus Compatible) Interface Vout POL 3 Readout of the ADC Trim Dynamic trimming/margining control Other Features Programmable analog circuitry Wide supply range, 2.8V to 3.96V 6 Analog 6 Analog Trim Outputs Monitor Inputs In-system programmable through JTAG Industrial temperature range: -40C to +85C ADC CPU 32-pin QFNS (Quad Flat-pack, No lead, Saw- 1 Power Supply singulated) package , only 5mm x 5mm, lead- Margin/Trim 2 2 I C free option I C Control Interface Bus Description ispPAC-POWR6AT6 Lattices Power Manager II ispPAC-POWR6AT6 is a general-purpose power-supply monitoring and margin- ing controller, incorporating in-system programmable 2 analog functions implemented in non-volatile E CMOS mode. The operating voltage profile can be selected technology. The ispPAC-POWR6AT6 device provides using external hardware pins. six independent analog input channels to monitor up to six power supply test points. Each of these input chan- The on-chip 10-bit A/D converter can both be used to 2 nels offers a differential input to support remote ground monitor the V voltage through the I C bus as well as MON sensing. for implementing digital closed loop mode for maintain- ing the output voltage of all power supplies controlled by The ispPAC-POWR6AT6 incorporates six DACs for gen- the monitoring and trimming section of the ispPAC- erating a trimming voltage to control the output voltage POWR6AT6 device. of a power supply. The trimming voltage can be set to 2 four hardware selectable preset values (voltage profiles) The I C bus/SMBus interface allows an external micro- or can be dynamically loaded in to the DAC through the controller to measure the voltages connected to the 2 I C bus. Additionally, each power supply output voltage V analog monitor inputs and load the DACs for the MON can be maintained within 1% tolerance across various generation of the trimming voltages of the external DC- load conditions using the Digital Closed Loop Control DC converters. 1. Use 32-pin QFNS package for all new designs. Refer to PCN 13A-08 for 32-pin QFN package discontinuance. 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 DS1016 01.5 Other Board CircuitryTMS TCK TDI TDO VCCJ GND ispPAC-POWR6AT6 Data Sheet Figure 3-1. ispPAC-POWR6AT6 Block Diagram VMON1 Decoder DAC TrimCell 1 TRIM1 VMON1GS VMON2 Set Point DAC TrimCell 2 TRIM2 Registers VMON2GS VMON3 DAC TrimCell 3 TRIM3 VMON3GS ADC Control Logic VMON4 DAC TrimCell 4 TRIM4 VMON4GS OSC VMON5 TrimCell 5 DAC TRIM5 VMON5GS VMON6 VMON6GS TrimCell 6 DAC TRIM6 SCL 2 I C Interface JTAG Interface SDA ispPAC-POWR6AT6 2 CLTENb CLTLOCK/SMBA VPS0 VPS1 VCCD VCCA