Data Sheet MxL7704 Five Output Universal PMIC General Description Features The MxL7704 is a five output Universal PMIC optimized for Input voltage range: 4.0V to 5.5V powering low power FPGAs, DSPs, and microprocessors 4 Synchronous Buck Regulators from 5V inputs. Four synchronous step down buck Internally compensated current mode regulators range from 1.5A system power to 4A core power. A 100mA LDO provides a clean 1.5V to 3.6V 1MHz to 2.1MHz switching frequency power for auxiliary devices. All outputs support 10% Buck 1: 3.0V to 3.6V, 20mV step, 1.5A margining and the two highest power outputs support dynamic voltage control to support processors that can Buck 2: 1.3V to 1.92V, 20mV step, 1.5A 2 utilize this function to save power. Through a 400kHz I C Buck 3: 0.8V to 1.6V, 6.25mV step, 2.5A interface, the customer can monitor an input voltage flag 2 and PGOOD flags for each output. The I C port can also Buck 4: 0.6V to 1.4V, 6.25mV step, 4A be used to modify power up and down sequencing options, 100mA LDO 1.5V to 3.6V, 20mV step assign PGOOD outputs to the PGOOD pins, enable 2% maximum total dc output error over line, load and outputs and select switching frequency. temperature High switching frequency and a current mode architecture 2 3.3V/5V 400kHz I C interface with internal compensation enable a very fast transient Dynamic voltage scaling response to line and load changes without sacrificing stability and keeping board space to a minimum. Status monitoring by channel Sequencing control Fault protection features include input undervoltage lockout, overcurrent protection, and thermal protection. Input voltage status register The MxL7704 is offered in a 5mm x 5mm QFN package. Highly flexible conditional sequencing engine with Two pre-programmed standard products are available. external input The MxL7704-X has been optimized for powering the 2 configurable PGOOD outputs Xilinx Zynq Ultrascale+ ZU2 and ZU3 MPSoCs. Adjustable switching frequency The bucks are pre-programmed to provide the core rail (0.85V up to 4A), DDR3L memory power (1.35V), I/O and 5mm x 5mm 32-pin QFN package system power (1.8V and 3.3V). Sequencing is tailored Two standard factory programmed devices to the unique needs of the ZU2 and ZU3 MPSoCs, MxL7704-A: IO rails up first, core last (1.2V) offering accelerated time to market with Xilinx Zynq Ultrascale+ ZU2 and ZU3 devices. The MxL7704-A MxL7704-X for Xilinx ZU2 and ZU3 MPSoCs is designed to power a wide range of ARM Cortex - based processors (A7, A9, and A53) which use a more Applications conventional sequencing scheme where the I/O rails power up first and core is last. The bucks provide the 1.2V Low power processor, ASIC and FPGA power core rail, 1.35V DDR3L power, 1.8V and 3.3V rails for I/O and system power. VTT is supported by the addition of Industrial control the XRP2997 DDR Bus Termination Regulator. Test equipment POS terminals Ordering Information - Back Page www.maxlinear.com Rev 1B REV1A i/iRevision History MxL7704 Data Sheet Revision History Revision Release Date Change Description 1A 2/28/18 Initial Release Added inductor value calculation to Minimum Effective C section. OUT 2 Updated Output Voltage Scaling and I C Operation sections and Register Descriptions 0x10 - 0x14. Updated ESD table. 1B 7/3/18 Added open drain to PG pin descriptions. Added sentence to PGOOD section and deleted sentence from Operations section about unassigned PG pin. Updated General Description and Features with -A and -X information. 7/3/18 Rev 1B ii