ST16C554 / ST16C554D / ST68C554 Data Sheet 2.97V to 5.5V Quad UARTs with 16-Byte FIFO General Description Features The ST16C554, ST16C554D and ST68C554 are each quad Pin-to-pin compatible with the industry standard Universal Asynchronous Receivers and Transmitters ST16C454, ST68C454, ST68C554, TIs TL16C554A and Philips SC16C554B (UARTs) with 16 bytes of transmit and receive FIFOs, selectable receive FIFO trigger levels, and data rates of up to Intel or Motorola data bus interface select 1.5Mbps. Each UART has a set of registers that provide the Four independent UART channels user with operating status and control, receiver error indications, and modem serial interface controls. An internal Register set compatible to 16C550 loopback capability allows onboard diagnostics. The Data rates of up to 1.5Mbps at 5V ST16C554 is available in a 64-pin LQFP package, the Data rates of up to 500kbps at 3.3V ST16C554D is available in both a 64-pin LQFP and a 68-pin 16 byte transmit FIFO PLCC package, and the ST68C554 is available in a 68-pin 16 byte receive FIFO with error tags PLCC package. The 64-pin package only offers the 16 mode 4 selectable RX FIFO trigger levels interface, but the 68-pin package offers an additional 68 Full modem interface mode interface which allows easy integration with Motorola processors. The ST16C554CQ64 (64-pin) offers three-state 2.97V to 5.5V supply operation interrupt output while the ST16C554DCQ64 provides Crystal oscillator or external clock input continuous interrupt output. The ST16C554 and ST16C554D combine the package interface modes of the 16C554 and 68C554 on a single integrated chip. Applications Portable appliances Ordering Information - page 32 Telecommunication network routers Ethernet network routers Cellular data devices Factory automation and process controls Block Diagram 2.97 V to 5.5 V VCC A2:A0 GND D7:D0 UART Channel A IOR 16 Byte TX FIFO UART TXA, RXA, IRTXA, DTRA , IOW Regs IR DSRA , RTSA , CTSA , TX & RX CSA ENDEC CDA , RIA BRG CSB 16 Byte RX FIFO CSC TXB, RXB, IRTXB, DTRB , CSD UART Channel B DSRB , RTSB , CTSB , (same as Channel A) INTA Data Bus CDB , RIB Interface INTB INTC TXC, RXC, IRTXC, DTRC , UART Channel C DSRC , RTSC , CTSC , (same as Channel A) INTD CDC , RIC TXRDY A-D TXD, RXD, IRTXD, DTRD , UART Channel D RXRDY A-D DSRD , RTSD , CTSD , (same as Channel A) Reset CDD , RID 16 68 / XTAL1 Crystal Osc Buffer INTSEL / XTAL2 Figure 1: ST16C554 Block Diagram www.maxlinear.com Rev 4.0.2 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet Revision History Revision History Document No. Release Date Change Description 3.3.0 August 2004 Added Revision History and Device Status. 3.3.1 August 2005 Updated the 1.4mm-thick Quad Flat Pack package description fromTQF toLQF to be consistent with JEDEC and Industry norms. 4.0.0 April 2006 New datasheet format. Changed active low signal designator from in front of signal name to after signal name. Updated AC Electrical Characteristics. 4.0.1 June 2006 Corrected Part Numbers in Ordering Information. 4.0.2 9/4/19 Update to MaxLinear format. Update Ordering Information and moved to end. Correct pin configuration with selectable 16/68 pin from ST16C554 to ST16C554D. 9/4/19 Rev 4.0.2 ii