ST16C580 UART WITH 16-BYTE FIFOs AND INFRARED (IrDA) ENCODER/DECODER August 2005 GENERAL DESCRIPTION 1 The ST16C580 is a universal asynchronous receiver and transmitter (UART) and is pin compatible with the ST16C550 UART. The 580 is an enhanced UART with 16 byte FIFOs, automatic hardware/software flow control, and data rates up to 1.5Mbps. Onboard status registers provide the user with error indications and operational status. Modem interface control is included and can be optionally configured to operate with the Infrared (IrDA) encoder/decoder. The system interrupts may be tailored to meet user requirements. An internal loop-back capability allows onboard diagnostics. The 580 is available in the 48 pin TQFP package. It is fabricated in an advanced CMOS process to achieve low drain power and high speed requirements. 48 Pin TQFP Package FEATURES Pin to pin and functionally compatible to the Industry N.C. 1 36 N.C. Standard 16550 D5 2 35 RESET 2.97 to 5.5 volt operation D6 3 34 -OP1 1.5 Mbps transmit/receive operation (24MHz) D7 4 33 -DTR 16 byte transmit FIFO RCLK 5 32 -RTS 16 byte receive FIFO with error flags -OP2 N.C. 6 31 Automatic hardware/software flow control XR16C580CQ48 RX 7 30 INT Programmable Xon/Xoff characters TX 8 29 -RXRDY Independent transmit and receive control 9 28 A0 CS0 Software selectable Baud Rate Generator pre- CS1 10 27 A1 scaleable clock rates of 1X or 4X -CS2 11 26 A2 Four selectable transmit/receive FIFO interrupt trig- 12 25 N.C. -BAUDOUT ger levels Standard modem interface or Infrared IrDA encode/ decoder interface Sleep mode ( 200A stand-by ) Low operating current ( 1.2mA typ.) ORDERING INFORMATION Part number Package Operating temp Device Status ST16C580CQ48 48-Lead TQFP 0 C to + 70 C Active ST16C580IQ48 48-Lead TQFP -40 C to + 85 C Active *Note 1 Covered by U.S. Patent 5,649,122. Rev. 1.22 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017 N.C. 13 48 N.C. XTAL1 47 D4 14 XTAL2 15 46 D3 45 -IOW 16 D2 IOW 17 44 D1 GND 18 43 D0 -IOR 42 VCC 19 IOR 20 41 -RI N.C. 21 40 -CD -DDIS 39 -DSR 22 -TXRDY 23 38 -CTS 37 -AS 24 N.C.ST16C580 Figure 2, BLOCK DIAGRAM Transmit Transmit FIFO Shift TX D0-D7 Registers Register -IOR,IOR -IOW,IOW RESET Flow Ir Control Encoder Logic A0-A2 Receive Receive -AS FIFO Shift RX CS0,CS1 Registers Register -CS2 -DDIS Flow Ir Control Decoder Logic INT -RXRDY -TXRDY -DTR,-RTS -OP1,-OP2 Modem -CTS Control -RI XTAL1 Logic -CD RCLK -DSR XTAL2 -BAUDOUT Rev. 1.22 2 Clock Interrupt Register Data bus & Control Select & Baud Rate Logic Logic Control Logic Generator Inter Connect Bus Lines & Control signals