XR16L2552 2.25V TO 5.5V DUART WITH 16-BYTE FIFO SEPTEMBER 2010 REV. 1.1.2 FEATURES GENERAL DESCRIPTION 2.25 to 5.5 Volt Operation The XR16L2552 (L2552) is a dual universal asynchronous receiver and transmitter (UART) with 5 5 Volt Tolerant Inputs volt tolerant inputs. The XR16L2552 is an improved Pin-to-pin and functionally compatible to National version of the ST16C2552 UART with lower operating PC16552 voltages and 5 volt tolerant inputs. The L2552 Pin-to-pin Compatible to Exars ST16C2552, provides enhanced UART functions with 16 byte TX XR16L2752 and XR16C2852 in the 44-PLCC and RX FIFOs, automatic hardware (RTS/CTS) and software (Xon/Xoff) flow control, and a complete 2 Independent UART Channels modem control interface. Onboard status registers Up to 3.125Mbps with external clock of 50 MHz provide the user with error indications and Register Set Compatible to 16C550 operational status. Indepedendent programmable 16 byte Transmit FIFO to reduce the bandwidth baud rate generators are provided to select transmit requirement of the external CPU and receive clock rates up to 3.125Mbps. An internal 16 byte Receive FIFO with error tags to reduce loop-back capability allows onboard diagnostics. The the bandwidth requirement of the external CPU L2552 provides block mode data transfers (DMA) through FIFO controls. DMA transfer monitoring is 4 selectable RX FIFO Trigger Levels provided through the signals TXRDY and RXRDY . Automatic RTS/CTS hardware flow control An Alternate Function Register provides the user with Automatic XonXoff software flow control the ability to write the control registers for both UARTs Wireless infrared encoder/decoder concurrently and selection of the Multi-Function Full Modem Interface (CTS , RTS , DSR , output (Baudout , OP2 , or RXRDY ). DTR , RI , CD ) NOTE: 1 Covered by U.S. Patent 5,649,122. Programmable character lengths (5, 6, 7, 8) APPLICATIONS with even, odd, or no parity Multi-Function output allows more package Portable Appliances functions with fewer I/O pins Telecommunication Network Routers Concurrent write to Channels A and B Ethernet Network Routers Crystal oscillator or external clock input Cellular Data Devices 48-TQFP (7x7x1.0 mm) and 44-PLCC packages Factory Automation and Process Controls FIGURE 1. XR16L2552 BLOCK DIAGRAM 2.25 to 5.5 Volt VCC * 5 Volt Tolerant Inputs A2:A0 GND D7:D0 IOR UART Channel A IOW TXA 16 Byte TX FIFO CS UART CHSEL Regs TX & RX INTA INTB BRG 16 Byte RX FIFO RXA TXRDY A/B 8-bit Data RXRDY A/B Bus TXB (48-TQFP Only) UART Channel B Interface (same as Channel A) RXB MFA (OP2A , BAUDOUTA , or XTAL1 Crystal Osc/Buffer RXRDYA ) XTAL2 MFB (OP2B , CTS A/B, RI A/B, BAUDOUTB , or Modem Control Logic CD A/B, DSR A/B RXRDYB ) Reset DTR A/B, RTS A/B 2552BLK Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XR16L2552 2.25V TO 5.5V DUART WITH 16-BYTE FIFO REV. 1.1.2 FIGURE 2. PIN OUT ASSIGNMENTS 48-TQFP PACKAGE D5 1 36 RXA D6 2 35 TXA DTRA D7 3 34 A0 4 33 RTSA XTAL1 5 32 MFA XR16L2552 6 31 RXRDYA GND 48-pin TQFP INTA XTAL2 7 30 RXRDYB 8 29 VCC 9 28 TXRDYB A1 RIB A2 10 27 CHSEL 11 26 CDB 44-PLCC PACKAGE INTB 12 25 DSRB D5 7 39 RXA D6 8 38 TXA D7 9 37 DTRA A0 10 36 RTSA 11 35 MFA XTAL1 XR16L2552 GND 12 34 INTA 44-pin PLCC XTAL2 13 33 VCC A1 14 32 TXRDYB A2 15 31 RIB CHSEL 16 30 CDB INTB 17 29 DSRB ORDERING INFORMATION OPERATING TEMPERATURE PART NUMBER PACKAGE DEVICE STATUS RANGE XR16L2552IM 48-Lead TQFP -40C to +85C Active XR16L2552IJ 44-Lead PLCC -40C to +85C Active 2 CS 13 48 D4 MFB 14 47 D3 IOW 15 46 D2 RESET 16 45 D1 GND 44 17 D0 RTSB 18 43 TXRDYA NC 19 42 VCC IOR 41 20 RIA RXB 21 40 CDA TXB 22 39 DSRA DTRB 38 23 CTSA CTSB 24 37 NC 18 6 CS D4 MFB 19 5 D3 IOW 20 4 D2 RESET 21 3 D1 GND 22 2 D0 23 RTSB 1 TXRDYA IOR 24 44 VCC 25 RXB 43 RIA TXB 26 42 CDA DTRB 27 41 DSRA CTSB 28 40 CTSA