XR16V564/564D 2.25V TO 3.6V QUAD UART WITH 32-BYTE FIFO JULY 2010 REV. 1.0.4 FEATURES GENERAL DESCRIPTION Pin-to-pin compatible with ST16C454, ST16C554, 1 The XR16V564 (V564) is an enhanced quad TIs TL16C754B and Philips SC16C754B Universal Asynchronous Receiver and Transmitter (UART) with 32 bytes of transmit and receive FIFOs, Intel or Motorola Data Bus Interface select programmable transmit and receive FIFO trigger Four independent UART channels levels, automatic hardware and software flow control, Register Set Compatible to 16C550 and data rates of up to 16 Mbps at 4X sampling rate. Each UART has a set of registers that provide the Data rates of up to 16 Mbps user with operating status and control, receiver error 32 byte Transmit FIFO indications, and modem serial interface controls. An 32 byte Receive FIFO with error tags internal loopback capability allows onboard 4 Selectable TX and RX FIFO Trigger Levels diagnostics. The V564 is available in a 48-pin QFN, 64-pin LQFP, 68-pin PLCC and 80-pin LQFP Automatic Hardware (RTS/CTS) Flow Control packages. The 64-pin and 80-pin packages only offer Automatic Software (Xon/Xoff) Flow Control the 16 mode interface, but the 48 and 68 pin Programmable Xon/Xoff characters packages offer an additional 68 mode interface which Wireless Infrared (IrDA 1.0) Encoder/Decoder allows easy integration with Motorola processors. The XR16V564IV (64-pin) offers three state interrupt Full modem interface output while the XR16V564DIV provides continuous 2.25V to 3.6V supply operation interrupt output. The XR16V564 is compatible with the industry standard ST16C554 and ST16C654/ Sleep Mode with automatic wake-up 654D. Crystal oscillator or external clock input NOTE: 1 Covered by U.S. Patent 5,649,122. APPLICATIONS Portable Appliances Telecommunication Network Routers Ethernet Network Routers Cellular Data Devices Factory Automation and Process Controls FIGURE 1. XR16V564 BLOCK DIAGRAM * 5 Volt Tolerant Inputs 2.25V to 3.6V VCC A2:A0 (Except XTAL1 input) GND D7:D0 UART Channel A IOR 32 Byte TX FIFO UART TXA, RXA, DTRA , IOW Regs IR DSRA , RTSA , CTSA , TX & RX CSA ENDEC CDA , RIA BRG CSB 32 Byte RX FIFO CSC TXB, RXB, DTRB , CSD UART Channel B DSRB , RTSB , CTSB , INTA (same as Channel A) Data Bus CDB , RIB INTB Interface INTC TXC, RXC, DTRC , UART Channel C INTD DSRC , RTSC , CTSC , (same as Channel A) CDC , RIC TXRDY A-D RXRDY A-D TXD, RXD, DTRD , UART Channel D Reset DSRD , RTSD , CTSD , (same as Channel A) CDD , RID 16/68 INTSEL XTAL1 Crystal Osc/Buffer CLKSEL XTAL2 564 BLK Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XR16V564/564D 2.25V TO 3.6V QUAD UART WITH 32-BYTE FIFO REV. 1.0.4 FIGURE 2. PIN OUT ASSIGNMENT FOR 68-PIN PLCC PACKAGES IN 16 AND 68 MODE AND 64-PIN LQFP PACKAGES DSRA 10 60 DSRD DSRA 10 60 DSRD CTSA 11 59 CTSD CTSA 11 59 CTSD DTRA 12 58 DTRD DTRA 12 58 DTRD VCC 13 57 GND VCC 13 57 GND RTSA 14 56 RTSD RTSA 14 56 RTSD IRQ 15 55 N.C. INTA 15 55 INTD CS 16 54 N.C. CSA 16 54 CSD XR16V564 XR16V564 TXA 17 53 TXD TXA 17 53 TXD 68-pin PLCC 68-pin PLCC R/W 18 52 VCC IOW 18 52 IOR Motorola Mode Intel Mode TXB 19 51 TXC 19 TXB 51 TXC (16/68 pin connected to GND) (16/68 pin connected to VCC) A3 20 50 A4 20 50 CSB CSC N.C. 21 49 N.C. INTB 21 49 INTC RTSB 22 48 RTSC RTSB 22 48 RTSC GND 23 47 VCC GND 23 47 VCC DTRB 24 46 DTRC DTRB 24 46 DTRC 25 45 CTSB 25 45 CTSC CTSB CTSC DSRB 26 44 DSRC DSRB 26 44 DSRC DSRA 1 48 DSRD CTSA 2 47 CTSD DTRA 3 46 DTRD VCC 4 45 GND RTSA 5 44 RTSD INTA 6 43 INTD CSA 7 42 CSD XR16V564 TXA 8 41 TXD 64-pin TQFP IOW 9 40 IOR Intel Mode Only TXB 10 39 TXC CSB 11 38 CSC INTB 12 37 INTC 13 36 RTSC RTSB GND 14 35 VCC DTRB 15 34 DTRC CTSB 16 33 CTSC 2 CDB 27 9 CDA RIB 28 8 RIA RXB 29 7 RXA CLKSEL 30 6 GND 16/68 31 5 D7 A2 32 4 D6 A1 33 3 D5 A0 34 2 D4 XTAL1 35 1 D3 XTAL2 36 68 D2 RESET 37 67 D1 RXRDY 38 66 D0 TXRDY 39 65 INTSEL DSRB 17 64 CDA GND 40 64 VCC RIA CDB 18 63 RXC 41 63 RXD RIB 19 62 RXA RIC 42 62 RID RXB 20 61 GND CDC 43 63 CDD CLKSEL 21 60 D7 A2 22 59 D6 A1 58 D5 23 A0 24 57 D4 XTAL1 25 56 D3 XTAL2 26 55 D2 RESET 27 54 D1 GND 28 53 D0 CDB 27 9 CDA RXC 29 52 VCC RIB 28 8 RIA RIC 30 51 RXD RXB 29 7 RXA CDC 31 50 RID CLKSEL 30 6 GND DSRC 32 49 CDD 16/68 31 5 D7 A2 32 4 D6 A1 33 3 D5 A0 34 2 D4 D3 XTAL1 35 1 D2 XTAL2 36 68 RESET 37 67 D1 RXRDY 38 66 D0 TXRDY 39 65 GND GND 40 64 VCC RXC 41 63 RXD RIC 42 62 RID CDC 43 63 CDD