XR20M1172L32-0A-EB MaxLinear

XTAL2 XTAL1 XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO JULY 2018 REV. 1.2.1 FEATURES GENERAL DESCRIPTION 1.62 to 3.6 Volt Operation 1 The XR20M1172 is a high performance two channel 2 universal asynchronous receiver and transmitter Selectable I C/SPI Interface (UART) with 64 byte TX and RX FIFOs and a SPI clock frequency up to 2 selectable I C/SPI slave interface. The XR20M1172 18 MHz at 3.3 V operates from 1.62 to 3.63 volts. The standard features include 16 selectable TX and RX FIFO 16 MHz at 2.5 V trigger levels, automatic hardware (RTS/CTS) and 8 MHz at 1.8 V software (Xon/Xoff) flow control, and a complete Full-featured UART modem interface. Onboard registers provide the user with operational status and data error flags. An Data rate of up to 16 Mbps at 3.3 V internal loopback capability allows system Data rate of up to 12.5 Mbps at 2.5 V diagnostics. Additional enhanced features includes a Data rate of up to 8 Mbps at 1.8 V programmable fractional baud rate generator and 8X Fractional Baud Rate Generator and 4X sampling rate that allows for a maximum baud rate of 16 Mbps at 3.3V. The XR20M1172 is available Transmit and Receive FIFOs of 64 bytes in the 32-pin QFN and 28-pin TSSOP packages. The 16 Selectable TX and RX FIFO Trigger Levels 32-pin QFN package has the EN485 and ENIR Automatic Hardware (RTS/CTS) Flow Control pins to allow the UART to power-up in the Auto Automatic Software (Xon/Xoff) Flow Control RS485 mode or the Infrared mode. Halt and Resume Transmission Control NOTE: 1 Covered by U.S. Patent 5,649,122 Automatic RS-485 Half-duplex Direction APPLICATIONS Control Output via RTS Portable Appliances Wireless Infrared (IrDA 1.0 and 1.1) Encoder/ Decoder Battery-Operated Devices Automatic sleep mode (< 30 uA at 3.3V) Cellular Data Devices General Purpose I/Os Factory Automation and Process Controls Full modem interface Crystal oscillator (up to 24MHz) or external clock (up to 64MHz) input 32-QFN and 28-TSSOP packages FIGURE 1. XR20M1172 BLOCK DIAGRAM VC C 1.62 V 3.63V C hannel 1 TX A 64 B yte RXA T X F IF O EN IR UART Regs EN 485 64 B yte RTSA CTSA RX FIFO IR Q RESET BR G SD A 2 SC K I C/ S P I GPIO 7: 0 GPIOs A0/C S In te rfa c e A1/SI TX B SO RXB U A R T C hannel 2 RTSB (S im ila r to C h a n n e l1 ) C rystal I2 C / S P I O sc / CTSB Buffer 1XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO REV. 1.2.1 FIGURE 2. PIN OUT ASSIGNMENT 24 23 22 21 20 19 18 17 CTSA 25 16 CTSB GPIO4/DSRA 26 15 RTSB GPIO6/CDA 27 14 GPIO3/RIB GPIO7/RIA 13 28 GPIO0/DSRB 32-pin QFN 29 VCC 12 GND 30 GPIO2/CDB A0/CS 11 31 XTAL2 A1/SI 10 SEL I2C SPI 32 9 XTAL1 1 23 4 56 78 28 GPIO7/RIA VCC 1 27 GPIO6/CDA A0/CS 2 GPIO4/DSRA 26 A1/SI 3 25 CTSA I2C/SPI 4 RESET 24 SO 5 23 GPIO1/DTRB SDA 6 22 GPIO5/DTRA RXB 7 28-Pin TSSOP 21 RTSA RXA 8 20 IRQ TXA 9 19 SCK TXB 10 18 CTSB XTAL1 11 17 RTSB XTAL2 12 GPIO3/RIB 16 GPIO2/CDB 13 15 GPIO0/DSRB GND 14 2 RESET N.C. GPIO1/DTRB SO GPIO5/DTRA SDA RTSA RXB IRQ RXA EN485 TXA ENIR TXB SCK N.C.