XRD98L23ACD-F MaxLinear

XRD98L23 8-Bit, High-speed Linear CIS/CCD Sensor Signal Processor with Serial Control November 2002-2 FEATURES APPLICATIONS 8-Bit Resolution, No Missing Codes Check Scanners One-channel 10MSPS Pixel Rate General Purpose CIS or CCD Imaging Dual-channel 5MSPS Pixel Rate Low Cost Data Acquisition Three-channel 3 MSPS Pixel Rate Simple and Direct Interface to Canon 600 DPI Sensors 6-bit Programmable Gain Amplifier 8-bit Programmable Offset Adjustment CIS or CCD Compatibility Internal Clamp for CIS or CCD AC Coupled Configurations 3.3V Operation & I/O Compatibility Serial Load Control Registers Low Power CMOS: 75mW-typ Low Cost 20-Lead Packages USB Compliant GENERAL DESCRIPTION The XRD98L23 is a complete linear CIS or CCD sensor CIS signal is level shifted to VRB in order to use the full signal processor on a single monolithic chip. The range of the ADC. In the CIS configuration the input can XRD98L23 includes a high speed 8-bit resolution ADC, also be AC coupled similar to the CCD configuration. a 6-bit Programmable Gain Amplifier with gain adjust- This enables CIS signals with large black levels to be ment of 1 to 10, and a typical 8-bit programmable input internally clamped to a DC reference equal to the black referred offset calibration range of 480mV. level. The DC reference is internally subtracted from the input signal. In the CCD configuration the input signal is AC coupled with an external capacitor. An internal clamp sets the The CIS configuration can also be used in other black level. In the CIS configuration, the clamp switch applications that do not require CDS function, such as can be disabled and the CIS output signal is DC low cost data acquisition. coupled from the CIS sensor to the XRD98L23. The ORDERING INFORMATION Package Type Temperature Range Part Number 20-Lead SOIC 0C to +70C XRD98L23ACD 20-Lead SSOP 0C to +70C XRD98L23ACU Rev. 1.00 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.comXRD98L23 VBG CIS REF Circuit AVDD Power Down CIS REF Circuit RED Triple S/H DVDD & GRN + 3-1 VREF+ VRT MUX BUFFER BLU 8 8 DATA 8-BIT RL PGA I/O DB7:0 ADC DC Reference PORT V DCREF VDCEXT VRB INT/EXT V DCREF 6 G<5:0> DGND CLP 6-BIT GAIN AVDD REGISTERS Power DC/AC Down R G B AGND AGND 8-BIT DAC AGND SYNCH 8 O<7:0> CIS/CCD CLAMP 8-BIT OFFSET REGISTERS TIMING ADCCLK & VRT R G B CIS CONTROL LOGIC CCD Figure 1. Functional Block Diagram Rev. 1.00 2 CLAMP