PGND2 BST3 31 20 BST3 BST1 GH3 32 19 GH3 GH1 LX3 33 18 LX3 LX1 GL3 34 17 GL3 GL1 PGND3 35 16 PGND3 PGND1 VOUT4 36 15 VOUT4 1V VCCA VOUT3 37 14 VOUT3 2.5V VIN2 VOUT2 38 13 VOUT2 1.8V VIN1 VOUT1 39 12 FB VOUT1 LDO AGND 40 11 XXRRPP77771144EEVVBB--DDEEMMOO--XX FFoouurr CChhaannnneell DDiiggiittaall PPWWMM DDeemmoo BBooaarrddss s April 2011 Rev. 1.0.0 GENERAL DESCRIPTION EVALUATION BOARD MANUAL EVALUATION BOARD MANUAL The XRP7714EVB-DEMO-1, XRP7714EVB- DEMO-2, and the XRP7714-DEMO-2P Demo boards are complete, working, four channel, power systems measuring either 2 x 2, or 2 by 2.5 capable of producing over 35 watts. They provide 3.3V, 2.5V 1.8V and 1V at a maximum of 4 amps per channel. The 2.5V, 1.8V and 1V supplies can be adjusted in 50mV increments, and the 3.3V supply is adjustable in 100mV increments. The order and ramp rates for each supply can be programmed to accommodate any sequencing requirement. All XRP7714EVB-DEMO-1 XRP7714EVB-DEMO-2/2P power supply operations can be controlled 2 over an I C interface. Faults, output voltages FEATURES and currents can also be monitored. Four GPIO signals are available and can be XRP7714 Programmable Controller programmed to provide status of power good 4 Channel Power System signals enables and faults. Unused GPIO pins can be programmed as I/O expansion for a Wide Input Voltage Range: 4.5V-25V microcontroller. The board is supported by TM Over 35W Capable PowerArchitect and plugs directly onto the Exar Communications Module (XRP77xxEVB- Small Form Factor: 2.0 x 2.0 XCM). 2 I C Interface Programming Monitoring Control EVALUATION BOARD VIN CSD1 CON3 R28 R1 SD101AWS 1 VCCA VCCD VIN 3 VIN1 C8 0.00 4.99 Q1A 2 C1 C17 C18 LX1 .01uF 50V VOUT1 3.3V L1 10uF 35V 2.2uF 10V 2.2uF 10V 4.9uH R2 R13 R6 VOUT1 3.3V FDS8984 VOUT1 0 0 0.00 GND R5 4.99 CSD1 CSD1 R3 FDS8984 VIN1 C6 4.99 Q1B C11 C10 C12 FB VOUT1 VIN1 10uF 35V 47uF 10V 47uF 16V .1uF 50V TIP8 R7 CSD1 C9 R4 DNP C2 1000pF 50V CSD1 TIP4 GH1 4.99 470uF 35V CSD1 PGND1 D2 LDO TIP5 GL1 BST2 VCCD VIN CSD1 SD101AWS VIN1 C3 C23 CON4 2.2uF 10V C16 Q2B .01uF 50V LX2 VOUT2 1.8V TIP6 GPIO5 SCL L2 3 .1uF 50V GPIO4 SDA 2 3.3uH CSD1 1 C13 FDS8984 VOUT2 1.8V VOUT2 U1 R12 CON4 4.99 R10 FDS8984 CSD1 .1uF 50V 1 30 GL2 C20 4.99 Q2A C26 C25 C27 AVDD GL2 10uF 35V 150uF 10V47uF 16V .1uF 50V TIP10 2 29 LX2 DVDD LX2 C24 R11 CSD1 GPIO0 3 28 GH2 1000pF 50V GPIO0 GH2 GH2 4.99 GPIO1 4 27 BST2 GPIO1 BST2 PGND2 GPIO2 5 26 VCCD D3 GPIO2 VCCD GL2 VCCA BST3 VCCD CON5 VIN1 GPIO3 6 25 BST4 GPIO3 BST4 SD101AWS 10 ENABLE R15 GPIO4 SDA7 24 GH4 VIN1 C33 9 GPIO4 GH4 100K Q3B .01uF 50V 8 LX3 VOUT3 2.5V GPIO5 SCL 8 23 LX4 L3 7 GPIO5 LX4 6 4.9uH ENABLE 9 22 GL4 5 ENABLE GL4 FDS8984 VOUT3 2.5V 4 TIP11 GPIO4 SDA 10 21 PGND4 R20 3 C28 DGND PGND4 4.99 R18 2 FDS8984 CSD1 GPIO5 SCL 1 .01uF 50V C31 4.99 Q3A C37 C36 C38 XRP7714 10uF 35V 47uF 10V 47uF 16V .1uF 50V TIP14 CON5 C35 R19 CSD1 1000pF 50V GH3 4.99 PGND3 D4 GPIO0 GPIO1 GPIO2 GPIO3 GL3 CSD1 CSD1 CSD1 CSD1 BST4 VCCD 1000pF 50V 1000pF 50V C29 C39 C40 C41 SD101AWS 1000pF 50V 1000pF 50V VIN1 C34 Q4B .01uF 50V LX4 VOUT4 1V L4 2.0uH GPIO0 VOUT4 1V FDS8984 VOUT4 R25 GPIO1 4.99 R23 FDS8984 CSD1 CON9 CON10 CON11 CON12 C43 4.99 Q4A C45 C46 C47 GPIO2 MTG HOLE MTG HOLE MTG HOLE MTG HOLE 10uF 35V 330uF 4V 47uF 16V .1uF 50V TIP13 C44 GPIO3 R24 CSD1 1000pF 50V GH4 4.99 PGND4 GL4 Fig. 1: XRP7713EVB-DEMO-1 Schematic Exar Corporation www.exar.com 48720 Kato Road, Fremont CA 94538, USA Tel. +1 510 668-7000 Fax. +1 510 668-7001 LDO VCCA PGND1 GL1 LX1 GH1 BST1 PGND2XXRRPP77771144EEVVBB--DDEEMMOO--XX FFoouurr CChhaannnneell DDiiggiittaall PPWWMM DDeemmoo BBooaarrddss PIN ASSIGNMENT Fig. 2: XRP7714 Pin Assignment Pin Description Name Pin Number Description Power source for the internal linear regulators to generate VCCA, VDD and the Standby LDO (LDOOUT). Place a decoupling capacitor close to the controller IC. Also used in 39 VIN1 UVLO1 fault generation if VIN1 falls below the user programmed limit, all channels are shut down. The VIN1 pin needs to be tied to VIN2 on the board with a short trace. If the Vin2 pin voltage falls below the user programmed UVLO VIN2 level all channels are 38 VIN2 shut down. The VIN2 pin needs to be tied to VIN1 on the board with a short trace. Output of the internal 5V LDO. This voltage is internally used to power analog blocks. Note 37 VCCA that a compensation capacitor should be used on this pin (see application note). Gate Drive input voltage. This is not an output voltage. This pin can be connected to VCCA to provide power for the Gate Drive. VCCD should be connected to VCCA with the 26 VCCD shortest possible trace and decouple with a minimum 1F capacitor. Alternatively, VCCD could be connected to an external supply (not greater than 5V). Power Ground. Ground connection for the low side gate driver. Connect at low side FET 36,31,16,21 PGND1 4 source. Output of the internal 1.8V LDO. A decoupling capacitor should be placed between AVDD 1 AVDD and AGND close to the chip (with short traces). 2 DVDD Input for powering the internal digital logic. This pin should be connected to AVDD. Digital Ground. Connect this pin to the ground plane at the exposed pad with a separate 10 DGND trace. Analog Ground. Connect this pin to the ground plane at the exposed pad with a separate 11 AGND trace Output pin of the low side gate driver. Connect directly to the respective gate of an 35,30,17,22 GL1-GL4 external N-channel MOSFET. 2011 Exar Corporation 2/16 Rev. 1.0.0