XRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR JUNE 2006 REV. 1.0.1 provides a variety of loop-back and diagnostic GENERAL DESCRIPTION features as well as transmit driver short circuit The XRT83L30 is a fully integrated single-channel detection and receive loss of signal monitoring. It long-haul and short-haul line interface unit for supports internal impedance matching for 75, 100, T1(1.544Mbps) 100, E1(2.048Mbps) 75 or 120 110 and 120 for both transmitter and receiver. For and J1 110 applications. the receiver this is accomplished by internal resistors or through the combination of one single fixed value In long-haul applications the XRT83L30 accepts external resistor and programmable internal resistors. signals that have passed through cables from 0 feet In the absence of the power supply, the transmit to over 6000 feet in length and have been attenuated output and receive input are tri-stated allowing for by 0 to 45dB at 772kHz in T1 mode or 0 to 43dB at redundancy applications. The chip includes an 1024kHz in E1 mode. In T1 applications, the integrated programmable clock multiplier that can XRT83L30 can generate five transmit pulse shapes synthesize T1 or E1 master clocks from a variety of to meet the short-haul Digital Cross-Connect (DSX-1) external clock sources. template requirements as well as for Channel Service Units (CSU) Line Build Out (LBO) filters of 0dB, APPLICATIONS -7.5dB, -15dB and -22.5dB as required by FCC rules. T1 Digital Cross-Connects (DSX-1) It also provides programmable transmit pulse generator that can be used for arbitrary output pulse ISDN Primary Rate Interface shaping allowing performance improvement over a CSU/DSU E1/T1/J1 Interface wide variety of conditions. T1/E1/J1 LAN/WAN Routers The XRT83L30 provides both Serial Host microprocessor interface and Hardware Mode for Public switching Systems and PBX Interfaces programming and control. Both B8ZS and HDB3 T1/E1/J1 Multiplexer and Channel Banks encoding and decoding functions are included and can be disabled as required. On-chip crystal-less jitter FEATURES attenuator with a 32 or 64 bit FIFO can be placed (See Page 2) either in the receive or the transmit path with loop bandwidths of less than 3Hz. The XRT83L30 FIGURE 1. BLOCK DIAGRAM OF THE XRT83L30 T1/E1/J1 LIU (HOST MODE) MCLKE1 MCLKOUT MASTER CLOCK SYNTHESIZER MCLKT1 TAOS DRIVE DMO TXTEST 0:2 ENABLE MONITOR INSBPV QRSS TTIP TPOS / TDATA HDB3/ TX FILTER PATTERN TX/RX JITTER TIMING LINE B8ZS & PULSE TNEG / CODES GENERATOR ATTENUATOR CONTROL DRIVER ENCODER SHAPER TCLK TRING LBO 3:0 TXON LOCAL QRSS ENABLE ANALOG REMOTE DIGITAL LOOPBACK LOOPBACK LOOPBACK LOOPBACK QRSS QRPD ENABLE DETECTOR RCLK HDB3/ TIMING & PEAK TX/RX JITTER RX RTIP RNEG / LCV B8ZS DATA DETECTOR ATTENUATOR EQUALIZER RRING DECODER RECOVERY & SLICER RPOS / RDATA NETWORK LOS AIS NLCD LOOP NLCD ENABLE EQUALIZER DETECTOR DETECTOR DETECTOR CONTROL RLOS AISD TEST ICT HW/HOST SDO CS Serial Interface SCLK INT SDI RESET Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com JA SELECTXRT83L30 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 FIGURE 2. BLOCK DIAGRAM OF THE XRT83L30 T1/E1/J1 LIU (HARDWARE MODE) MCLKE1 MCLKOUT MASTER CLOCK SYNTHESIZER MCLKT1 CLKSEL 2:0 TAOS DRIVE TXTEST 0:2 DFM DMO ENABLE MONITOR INSBPV QRSS TPOS / TDATA TTIP HDB3/ TX FILTER PATTERN TX/RX JITTER TIMING LINE B8ZS & PULSE TNEG / CODES GENERATOR ATTENUATOR CONTROL DRIVER ENCODER SHAPER TCLK TRING LBO 3:0 LOCAL TXON QRSS ENABLE ANALOG REMOTE DIGITAL LOOPBACK LOOPBACK LOOPBACK LOOPBACK QRSS QRPD ENABLE DETECTOR RCLK HDB3/ TIMING & PEAK RTIP TX/RX JITTER RX B8ZS DATA DETECTOR RNEG / LCV ATTENUATOR EQUALIZER RRING DECODER RECOVERY & SLICER RPOS / RDATA LOOP1 NETWORK EQUALIZER LOS AIS LOOP0 LOOP NLCD ENABLE NLCD DETECTOR DETECTOR CONTROL DETECTOR AISD RLOS TEST ICT HW/HOST JABW GAUGE TRATIO JASEL1 SR/DR JASEL0 RXTSEL EQC 4:0 HARWARE CONTROL TCLKE TXTSEL TERSEL1 RCLKE RXMUTE TERSEL0 ATAOS RXRES1 RESET RXRES0 FEATURES Fully integrated single-channel long-haul and short-haul transceiver for E1,T1 or J1 applications. Adaptive Receive Equalizer for cable attenuation of up to 45dB for T1 and 43dB for E1. Programmable Transmit Pulse Shaper for E1,T1 or J1 short-haul interfaces. Five fixed transmit pulse settings for T1 short-haul applications plus a fully programmable waveform generator for transmit output pulse shaping. Programmable Transmit Line Build-Outs (LBO) for T1 long-haul application from 0dB to -22.5dB in three 7.5dB steps. Tri-State transmit output and receive input capability for redundancy applications Selectable receiver sensitivity from 0 to 36dB or 0 to 45dB cable loss for T1 772kHz and 0 to 43dB for E1 1024kHz. High receiver interference immunity Receive monitor mode handles 0 to 29dB resistive attenuation along with 0 to 6dB of cable attenuation for both T1 and E1 modes. Supports 75 and 120 (E1), 100 (T1) and 110 (J1) applications. Internal and external impedance matching for 75,100, 110 and 120. Transmit return loss meets or exceeds ETSI 300 166 standard On-chip digital clock recovery circuit for high input jitter tolerance Crystal-less digital jitter attenuator with 32-bit or 64-bit FIFO Selectable either in transmit or receive path On-chip frequency multiplier generates T1 or E1 Master clocks from variety of external clock sources On-chip transmit short-circuit protection and limiting, and driver fail monitor output (DMO) 2 JA SELECT