XRT83VSH316 16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT AUGUST 2017 REV. 1.0.3 for external timing (8kHz, 1.544Mhz, 2.048Mhz, GENERAL DESCRIPTION nxT1/J1, nxE1). The XRT83VSH316 is a fully integrated 16-channel Additional features include System Side LOS, AIS, short-haul line interface unit (LIU) that operates from QRSS/PRBS and Line Side RLOS, AIS, QRSS/ a 1.8V Inner Core and 3.3V I/O power supplies. PRBS, DMO with 16-bit LCV counters and diagnostic Using internal termination, the LIU provides one bill of loopback modes for each channel. materials to operate in T1, E1, or J1 mode APPLICATIONS independently on a per channel basis with minimum external components. The LIU features are T1 Digital Cross Connects (DSX-1) programmed through a standard parallel ISDN Primary Rate Interface microprocessor interface or SPI (Serial Mode). MaxLinears LIU has patented high impedance CSU/DSU E1/T1/J1 Interface circuits that allow the transmitter outputs and receiver T1/E1/J1 LAN/WAN Routers inputs to be high impedance when experiencing a Public Switching Systems and PBX Interfaces power failure or when the LIU is powered off. Key design features within the LIU optimize 1:1 or 1+1 T1/E1/J1 Multiplexer and Channel Banks redundancy and non-intrusive monitoring applications Integrated Multi-Service Access Platforms (IMAPs) to ensure reliability without using relays. Integrated Access Devices (IADs) The on-chip clock synthesizer generates T1/E1/J1 Inverse Multiplexing for ATM (IMA) clock rates from a selectable external clock frequency Wireless Base Stations and has five output clock references that can be used FIGURE 1. BLOCK DIAGRAM OF THE XRT83VSH316 Channel N of 16 RCLK B8ZS/HDB3 32-bit/64-bit Clock & Data Peak Detector RTIP RPOS Decoder Jitter Attenuator Recovery(C DR) & Slicer RRING RLOS PRBS RxON Line Detector System Generator AIS, RLOS, SAIS, SLOS, SPRBS LCV RxTSEL RNEG/LCV MUX Digital Remote Analog Loop Back Loop Back Loop Back Line Generator System Detector PRBS SAIS, SLOS, SPRBS DMO DMO TCLK TTIP B8ZS/ HDB3 32-bit/64-bit Timing Tx Pulse Shaper Line Driver TPOS Jitter Attenuator Control Encoder TRING TNEG TxON SLOS AIS JTAG Parallel SPI PLL MCLKnOUT Test Microprocessor Microprocessor 1 JTAG TEST GPIO 2:1 DATA 7:0 ADDR 9:0 PTYPE 2:0 CSdec 2:0 RD WR ALE PCLK RDY INT SER/PAR CS SDI SCLK SDO MCLKINXRT83VSH316 16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 FEATURES Fully integrated 16-Channel short haul transceivers for T1/J1 (1.544MHz) and E1 (2.048MHz) applications Parallel or SPI Microprocessor Interface T1/E1/J1 short haul and clock rate are per port selectable through software without changing components Internal Impedance matching on both receive and transmit for 75 (E1), 100 (T1), 110 (J1), and 120 (E1) applications are per port selectable through software without changing components Power down on a per channel basis with independent receive and transmit selection Five pre-programmed transmit pulse settings for T1 short haul applications per channel User programable Arbitrary Pulse mode for T1 and E1 On-Chip transmit short-circuit protection and limiting protects line drivers from damage on a per channel basis Crystal-Less digital jitter attenuators (JA) with 32-Bit or 64-Bit FIFO for the receive or transmit path per channel Driver failure monitor output (DMO) alerts of possible system or external component problems Transmit outputs and receive inputs may beHig impedance for protection or redundancy applications on a per channel basis Support for automatic protection switching 1:1 and 1+1 protection without relays Receive monitor mode handles 0 to 6dB resistive attenuation (flat loss) along with 0 to 6dB cable loss for both T1 and E1 Loss of signal (LOS) according to ITU-T G.775/ETS300233 (E1) and ANSI T1.403 (T1/J1) for system (SLOS) and line (RLOS) side diagnostics Programmable data stream muting upon RLOS detection On-Chip HDB3/B8ZS encoder/decoder with an internal 16-bit LCV counter for each channel On-Chip digital clock recovery circuit for high input jitter tolerance QRSS/PRBS pattern generator and detection for testing and monitoring for system (SPRBS) and line (PRBS) side diagnostics Error and bipolar violation insertion and detection Transmit all ones (TAOS) Generators and Detectors for system (SAIS) and line (AIS) side diagnostics Supports local analog, remote, digital, and dual loopback modes Supports gapped clocks for mapper/multiplexer applications 1.8V Digital Core 3.3V I/O and Analog Core 316-Pin STBGA package -40C to +85C Temperature Range (1) PRODUCT ORDERING INFORMATION PACKAGING PRODUCT NUMBER OPERATING TEMPERATURE RANGE PACKAGE TYPE LEAD-FREE METHOD 316 Shrink Thin Ball Grid Array o o (2) XRT83VSH316IB-F Tray -40 C to +85 C Yes (21.0 mm x 21.0 mm, STBGA) NOTE: 1. Refer to www.exar.com/XRT83VSH316 for most up-to-date Ordering Information. 2. Visit www.exar.com for additional information on Environmental Rating. 2