1282.1601 is a license-limited part of Mentor’s IT Design Tools. It provides support for engineers who are developing and designing PC-based systems. It also supports system integration and software test, debug, and analysis. The software includes graphical user interfaces, libraries of predefined components, wizards, and support for multiple file formats and standards such as EDIF, VHDL, Verilog AMS, and TCL scripting languages. It also provides connectivity to online networks such as Ethernet/IP, USB, RS485/UART/CAN, and Profinet. In addition, it offers signal integrity analysis, routing optimization, PCB layout, clock optimization, an integrated FPGA design flow, and simulation support for Verilog and VHDL.
