25CSM04 4-Mbit SPI Serial EEPROM with 128-Bit Serial Number and Enhanced Write Protection Features Package Types (not to scale) 4-Mbit Serial EEPROM: - 524,288 x 8 organization 8-Lead SOIC - Page size of 256 bytes CS 1 8 VCC - Byte or sequential reads SO 2 7 HOLD - Byte or page writes WP 3 6 SCK - Self-timed write cycle (5 ms maximum) Security Register: VSS 4 5 SI - Preprogrammed 128-bit serial number - 256-byte user-programmable lockable ID page 8-Ball CSP 8-Pad TDFN-S Built-in Error Correction Code (ECC) Logic: 1 8 CS VCC - ECC Status bit via the STATUS register VCC CS 2 7 SO HOLD JEDEC SPI Manufacturer Read ID Support 3 6 HOLD High-Speed Clock Frequency: SO WP SCK - 8 MHz at VCC 3.0V 4 5 VSS SI SCK WP - 5 MHz at VCC 2.5V Legacy Write Protection Mode: SI VSS - Block protection functionality (quarter, half or entire memory array) Enhanced Write Protection Mode: - User-definable memory partitions Pin Function Table - Each partition can be set independently and Name Function have unique protection behavior CS Chip Select Input Low-Power CMOS Technology: - Voltage range: 2.5V to 5.5V SO Serial Data Output - Write current: 3.0 mA at 5.0V WP Write-Protect Pin - Read current: 3.0 mA at 5.0V, 8 MHz VSS Ground - Standby current: 1.0 A at 2.5V (I-Temp.) SI Serial Data Input High Reliability: SCK Serial Clock Input - More than one million erase/write cycles HOLD Hold Input - Built-in ECC logic for increased reliability VCC Supply Voltage - Data retention: >100 years - ESD protection: >4000V Available Temperature Ranges: - Industrial (I): -40C to +85C Packages 8-Lead SOIC, 8-Pad TDFN-S and 8-Ball CSP packages 2019-2022 Microchip Technology Inc. and its subsidiares DS20005817D-page 125CSM04 The user-programmable section of the Security General Description register can later be permanently write-protected via a The Microchip Technology Inc. 25CSM04 provides software sequence. 4-Mbits of Serial EEPROM utilizing the Serial The 25CSM04 features a configurable write protection Peripheral Interface (SPI) compatible bus. The device scheme which allows the user to select Legacy Write is organized as 524,288 bytes of 8bits each Protection mode or Enhanced Write Protection mode. (512 Kbyte) and is optimized for use in consumer and Legacy Write Protection mode enables the Block industrial applications where reliable and dependable Protection function via the STATUS register. Enhanced nonvolatile memory storage is essential. The Write Protection mode segments the memory into 25CSM04 is capable of operation across a broad independent partitions. Each partition can be voltage range (2.5V to 5.5V). configured to inhibit writing based on the status of the The bus signals required are a clock input (SCK) plus Memory Partition register setting. separate data in (SI) and data out (SO) lines. Access to For added reliability the 25CSM04 uses a built-in Error ) the device is controlled through a Chip Select (CS Correction Code (ECC) scheme. This scheme can input. Communication to the device can be paused via correct up to one incorrectly read bit within four bytes the HOLD pin. While the device is paused, transitions read out. Additionally, the 25CSM04 includes a flag in on its inputs will be ignored, with the exception of Chip the STATUS register to report if any errors were Select, allowing the host to service higher priority detected and corrected in the most recent memory interrupts. array read sequence. The 25CSM04 features a nonvolatile Security register The 25CSM04 features an identification register that independent of the 4 Mbit main memory array. The first contains identification information that can be read half of the Security register is read-only and contains a from the device. This enables the application to factory-programmed, globally unique 128-bit serial electronically query and identify the 25CSM04 while it number in the first 16 bytes. The 128-bit serial number is in the system. The identification method and the is unique across the entire CS series of Serial standard instruction opcode comply with the JEDEC EEPROM products and eliminates the time consuming for Manufacturer and Device ID Read Methodology for step of performing and ensuring serialization of a SPI Compatible Serial Interface Memory Devices. The product on a manufacturing line. The 128-bit read-only type of information that can be read from the device serial number is followed by an additional 256 bytes of includes the JEDEC defined Manufacturer ID, the user-programmable EEPROM. vendor-specific Device ID, and the vendor-specific Extended Device Information (EDI). Bus Connections for the 25CSM04 Client 0 Client 1 Client 2 Client 3 DS20005817D-page 2 2019-2022 Microchip Technology Inc. and its subsidiares