47L64 2 64-Kbit I C EERAM Serial SRAM Features Package Types (not to scale) Unlimited Reads/Unlimited Writes: 8-Lead SOIC (Top View) - Standard serial SRAM protocol - Symmetrical timing for reads and writes VCAP 1 8 VCC SRAM Array: A1 2 7 WP - 8,192 x 8 bits A2 3 6 SCL 2 High-Speed I C Interface: VSS 4 5 SDA - Industry standard: 1 MHz, 400 kHz, and 100 kHz (1) TDFN - Zero cycle delay writes and reads to SRAM (Top View) array - Schmitt Trigger inputs for noise suppression VCAP 1 8 VCC Low-Power CMOS Technology: A1 2 7 WP - Active current: 1 mA (maximum) A2 SCL 3 6 - Standby current: 200 A (maximum) VSS SDA 4 5 Hidden EEPROM Backup Features Note 1: Includes Exposed Thermal Pad (EP) Cell-Based Nonvolatile Backup: - Mirrors SRAM array cell-for-cell Pin Descriptions - Transfers all data to/from SRAM cells in parallel (all cells at same time) Pin Name Description Invisible-to-User Data Transfers: VCAP External Capacitor - VCC level monitored inside device A1, A2 Hardware Address Pins - SRAM automatically saved on power disrupt VSS Ground - SRAM automatically restored on VCC return SCL Serial Clock Input 100,000 Backups Minimum SDA Serial Data Input/Output 100 Years Retention (at 55C) WP Write-Protect Input VCC Power Supply Other Features of the 47L64 Operating Voltage Range: 2.7V to 3.6V Temperature Ranges: - Industrial (I): -40C to +85C ESD protection: >2,000V Packages 8-Lead SOIC 8-Lead TDFN 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 147L64 General Description Powering the Device During SRAM to EEPROM Backup (VCAP) The Microchip Technology Inc. 47L64 serial EERAM has an SRAM memory core with hidden EEPROM A small capacitor (typically 22 F) is required for the backup. The device can be treated by the user as a full proper operation of the device. This capacitor is placed symmetrical read/write SRAM. Backup to EEPROM is between VCAP (pin 1) and the system VSS (see Normal handled by the device on any power disrupt, so the Device Operation). When power is first applied to the user can effectively view this device as an SRAM that device, this capacitor is charged to VCC through the never loses its data. device (see Normal Device Operation). During normal SRAM operation, the capacitor remains charged to The device is structured as a 64-Kbit SRAM with VCC and the level of system VCC is monitored by the EEPROM backup in each memory cell. The SRAM is 2 device. If system VCC drops below a set threshold, the organized as 8,192 x 8 bits and uses the I C serial 2 device interprets this as a power-off or brown-out interface. The I C bus uses two signal lines for event. The device suspends all I/O operation, shuts off communication: clock input (SCL) and data (SDA). its connection with the VCC pin, and uses the saved Access to the device is controlled through a chip energy in the capacitor to power the device through the address and address pins, allowing up to four devices VCAP pin as it transfers all SRAM data to EEPROM to share the same bus. (see Vcc Power-Off Event). On the next power-up of The SRAM is a conventional serial SRAM: it allows VCC, the data is transfered back to SRAM, the symmetrical reads and writes and has no limits on cell capacitor is recharged, and the SRAM operation usage. The backup EEPROM is invisible to the user continues. and cannot be accessed by the user independently. The device includes circuitry that detects VCC Normal Device Operation dropping below a certain threshold, shuts its connection to the outside environment, and transfers V (pin 8) System V CC CC all SRAM data to the EEPROM portion of each cell for V Monitor safe keeping. When VCC returns, the circuitry CC automatically returns the data to the SRAM and the V (pin ) CAP users interaction with the SRAM can continue with the same data set. C Charged to V VCAP CC Normal SRAM Block Diagram 6&/ V (pin 4) Operation SS 6 VCC Power :3 Control VCAP Block System V SS Memory Address and Data Control SDA 2 I C Control Logic Logic SCL VCC Power-Off Event and Address WP Decoder A1 V (pin 8) System V CC CC A2 Automatic Backup EEPROM V (pin ) CAP 8K x 8 EEPROM C Temporary V VCAP CC SRAM SRAM 8K x 8 SRAM to STORE V (pin 4) 6&/ SS EEPROM RECALL 6 Transfer :3 System V SS 2019-2020 Microchip Technology Inc. Preliminary DS20006168B-page 2