48L256 256-Kbit SPI Serial EERAM Serial SRAM Features Package Types (not to scale) Unlimited Reads/Unlimited Writes: 8-Lead SOIC - Standard serial SRAM protocol (Top View) - Symmetrical timing for reads and writes SRAM Array: CS 1 8 VCC - 32,768 x 8 bit SO 2 7 HOLD High-Speed SPI Interface: VCAP 3 6 SCK - Up to 66 MHz VSS 4 5 SI - Schmitt Trigger inputs for noise suppression Low-Power CMOS Technology: - Active current: 5 mA (maximum) Pin Function Table - Standby current: 300 A (at 85C maximum) - Hibernate current: 3 A (at 85C maximum) Name Function CS Chip Select Input Hidden EEPROM Backup Features SO Serial Data Output Cell-Based Nonvolatile Backup: VCAP External Capacitor - Mirrors SRAM array cell-for-cell VSS Ground - Transfers all data to/from SRAM cells in parallel (all cells at same time) SI Serial Data Input Invisible-to-User Data Transfers: SCK Serial Clock Input -VCC level monitored inside device HOLD Hold Input - SRAM automatically saved on power disrupt VCC Supply Voltage - SRAM automatically restored on VCC return 100,000 Backups Minimum (at 85C) 100 Years Retention (at 55C) Other Features of the 48L256 Operating Voltage Range: 2.7V-3.6V Temperature Ranges: - Industrial (I): -40C to +85C ESD Protection: >2,000V Packages 8-Lead SOIC 2019 Microchip Technology Inc. Preliminary DS20006237B-page 148L256 General Description Powering the Device During SRAM to EEPROM Backup (VCAP) The Microchip Technology Inc. 48L256 serial EERAM has an SRAM memory core with hidden EEPROM A small capacitor (typically 33 F) is required for the backup. The device can be treated by the user as a full proper operation of the device. This capacitor is placed symmetrical read/write SRAM. Backup to EEPROM is between VCAP (pin 3) and the system VSS (see Normal handled by the device on any power disrupt, so the Device Operation). When power is first applied to the user can effectively view this device as an SRAM that device, this capacitor is charged to VCC through the never loses its data. device (see Normal Device Operation). During normal SRAM operation, the capacitor remains charged to The device is structured as a 256-Kbit SRAM with VCC and the level of system VCC is monitored by the EEPROM backup in each memory cell. The SRAM is device. If system VCC drops below a set threshold, the organized as 32,768 x 8 bits and uses the SPI serial device interprets this as a power-off or brown-out interface. The SPI bus uses three signal lines for event. The device suspends all I/O operation, shuts off communication: clock input (SCK), data in (SI), and its connection with the VCC pin, and uses the saved data out (SO). Access to the device is controlled energy in the capacitor to power the device through the through a Chip Select (CS) input, allowing any number VCAP pin as it transfers all SRAM data to EEPROM of devices to share the same bus. (see Vcc Power-Off Event). On the next power-up of The SRAM is a conventional serial SRAM: it allows VCC, the data is transfered back to SRAM, the capaci- symmetrical reads and writes and has no limits on cell tor is recharged, and the SRAM operation continues. usage. The backup EEPROM is invisible to the user and cannot be accessed by the user independently. Normal Device Operation The device includes circuitry that detects VCC dropping below a certain threshold, shuts its V (pin 8) System V CC CC connection to the outside environment, and transfers V Monitor CC all SRAM data to the EEPROM portion of each cell for safe keeping. When VCC returns, the circuitry V (pin 3) CAP automatically returns the data to the SRAM and the C Charged to V users interaction with the SRAM can continue with the VCAP CC CS same data set. Normal SO SRAM SI V (pin 4) Operation SS SCK Block Diagram HOLD System V VCC Power SS Control VCAP Block VCC Power-Off Event Memory Address and Data Control CS V (pin 8) SPI Control Logic System V Logic CC CC SO Automatic and Address SI Backup Decoder SCK V (pin 3) CAP HOLD EEPROM C EEPROM Temporary V VCAP CC SRAM STATUS CS 32K x 8 Register SO SRAM to V (pin 4) SS SI EEPROM SRAM SCK Transfer STORE HOLD 32K x 8 System V SS RECALL 2019 Microchip Technology Inc. Preliminary DS20006237B-page 2