48L512/48LM01 512-Kbit/1-Mbit SPI Serial EERAM Serial SRAM Features Package Types (not to scale) Unlimited Reads/Unlimited Writes: - Standard serial SRAM protocol 8-Lead SOIC/SOIJ - Symmetrical timing for reads and writes (Top View) SRAM Array: - 65,536 x 8 bit (48L512) CS 1 8 VCC - 131,072 x 8 bit (48LM01) SO 2 7 HOLD High-Speed SPI Interface: VCAP 3 6 SCK - Up to 66 MHz VSS 4 5 SI - Schmitt Trigger inputs for noise suppression Low-Power CMOS Technology: - Active current: 5 mA (maximum) - Standby current: 200 A (at 85C maximum) Pin Function Table - Hibernate current: 3 A (at 85C maximum) Name Function Hidden EEPROM Backup Features CS Chip Select Input Cell-Based Nonvolatile Backup: SO Serial Data Output - Mirrors SRAM array cell-for-cell VCAP External Capacitor - Transfers all data to/from SRAM cells in parallel (all cells at same time) VSS Ground Invisible-to-User Data Transfers: SI Serial Data Input -VCC level monitored inside device SCK Serial Clock Input - SRAM automatically saved on power disrupt HOLD Hold Input - SRAM automatically restored on VCC return VCC Supply Voltage 100,000 Backups Minimum (at 85C) 100 Years Retention (at 55C) Other Features of the 48L512/48LM01 Operating Voltage Range: 2.7V-3.6V Temperature Ranges: - Industrial (I): -40C to +85C ESD Protection: >2,000V Packages 48L512: 8-Lead SOIC 48LM01: 8-Lead SOIJ 2018-2019 Microchip Technology Inc. DS20006008C-page 148L512/48LM01 General Description Powering the Device During SRAM to EEPROM Backup (VCAP) The Microchip Technology Inc. 48L512/48LM01 (48LXXX) serial EERAM has an SRAM memory core A small capacitor (typically 47 F to 100 F) is required with hidden EEPROM backup. The device can be for the proper operation of the device. This capacitor is treated by the user as a full symmetrical read/write placed between VCAP (pin 3) and the system VSS (see SRAM. Backup to EEPROM is handled by the device Normal Device Operation). When power is first applied on any power disrupt, so the user can effectively view to the device, this capacitor is charged to VCC through this device as an SRAM that never loses its data. the device (see Normal Device Operation). During nor- mal SRAM operation, the capacitor remains charged to The device is structured as a 512/1024-Kbit SRAM VCC and the level of system VCC is monitored by the with EEPROM backup in each memory cell. The device. If system VCC drops below a set threshold, the SRAM is organized as 65,536x8 bits or device interprets this as a power-off or brown-out 131,072x8bits, and uses the SPI serial interface. event. The device suspends all I/O operation, shuts off The SPI bus uses three signal lines for its connection with the VCC pin, and uses the saved communication: clock input (SCK), data in (SI), and energy in the capacitor to power the device through the data out (SO). Access to the device is controlled VCAP pin as it transfers all SRAM data to EEPROM ) input, allowing any number through a Chip Select (CS (see Vcc Power-Off Event). On the next power-up of of devices to share the same bus. VCC, the data is transfered back to SRAM, the capaci- The SRAM is a conventional serial SRAM: it allows tor is recharged, and the SRAM operation continues. symmetrical reads and writes and has no limits on cell usage. The backup EEPROM is invisible to the user Normal Device Operation and cannot be accessed by the user independently. The device includes circuitry that detects VCC V (pin 8) System V CC CC dropping below a certain threshold, shuts its V Monitor CC connection to the outside environment, and transfers all SRAM data to the EEPROM portion of each cell for V (pin 3) CAP safe keeping. When VCC returns, the circuitry C Charged to V automatically returns the data to the SRAM and the VCAP CC CS users interaction with the SRAM can continue with the Normal SO same data set. SRAM SI V (pin 4) Operation SS SCK HOLD Block Diagram System V SS VCC Power Control VCAP Block VCC Power-Off Event Memory Address V (pin 8) System V CC and Data Control CC Automatic CS SPI Control Logic Logic SO Backup and Address V (pin 3) SI CAP Decoder SCK EEPROM HOLD C Temporary V VCAP CC SRAM EEPROM CS 128K x 8 STATUS SO SRAM to 64K x 8 V (pin 4) SS SI Register EEPROM SCK Transfer SRAM HOLD 128K x 8 System V STORE SS 64K x 8 RECALL 2018-2019 Microchip Technology Inc. DS20006008C-page 2