48L640 64-Kbit SPI Serial EERAM Serial SRAM Features Package Types (not to scale) Unlimited Reads/Unlimited Writes: - Standard serial SRAM protocol 8-Lead SOIC (Top View) - Symmetrical timing for reads and writes SRAM Array: CS 1 8 VCC - 8,192 x 8 bit SO 2 7 HOLD High-Speed SPI Interface: VCAP 3 6 SCK - Up to 66 MHz VSS 4 5 SI - Schmitt Trigger inputs for noise suppression Low-Power CMOS Technology: - Active current: 5 mA (maximum) 8-Pad TDFN - Standby current: 200 A (at 85C maximum) (Top View) - Hibernate current: 3 A (at 85C maximum) CS 1 8 VCC Hidden EEPROM Backup Features 7 HOLD SO 2 VCAP 6 SCK 3 Cell-Based Nonvolatile Backup: 5 SI VSS 4 - Mirrors SRAM array cell-for-cell - Transfers all data to/from SRAM cells in parallel (all cells at same time) Invisible-to-User Data Transfers: Pin Function Table -VCC level monitored inside device Name Function - SRAM automatically saved on power disrupt CS Chip Select Input - SRAM automatically restored on VCC return 100,000 Backups Minimum (at 85C) SO Serial Data Output 100 Years Retention (at 55C) VCAP External Capacitor VSS Ground Other Features of the 48L640 SI Serial Data Input Operating Voltage Range: 2.7V-3.6V SCK Serial Clock Input Temperature Ranges: - Industrial (I): -40C to +85C HOLD Hold Input ESD protection: >2,000V VCC Supply Voltage Packages 8-Lead SOIC 8-Lead TDFN 2018-2019 Microchip Technology Inc. Preliminary DS20006055B-page 148L640 General Description Powering the Device During SRAM to EEPROM Backup (VCAP) The Microchip Technology Inc. 48L640 (48LXXX) serial EERAM has an SRAM memory core with hidden A small capacitor (typically 33 F) is required for the EEPROM backup. The device can be treated by the proper operation of the device. This capacitor is placed user as a full symmetrical read/write SRAM. Backup to between VCAP (pin 3) and the system VSS (see Normal EEPROM is handled by the device on any power Device Operation). When power is first applied to the disrupt, so the user can effectively view this device as device, this capacitor is charged to VCC through the an SRAM that never loses its data. device (see Normal Device Operation). During normal SRAM operation, the capacitor remains charged to The device is structured as a 64-Kbit SRAM with VCC and the level of system VCC is monitored by the EEPROM backup in each memory cell. The SRAM is device. If system VCC drops below a set threshold, the organized as 8,192 x 8 bits and uses the SPI serial device interprets this as a power-off or brown-out interface. The SPI bus uses three signal lines for event. The device suspends all I/O operation, shuts off communication: clock input (SCK), data in (SI), and its connection with the VCC pin, and uses the saved data out (SO). Access to the device is controlled energy in the capacitor to power the device through the through a Chip Select (CS) input, allowing any number VCAP pin as it transfers all SRAM data to EEPROM of devices to share the same bus. (see Vcc Power-Off Event). On the next power-up of The SRAM is a conventional serial SRAM: it allows VCC, the data is transfered back to SRAM, the capaci- symmetrical reads and writes and has no limits on cell tor is recharged, and the SRAM operation continues. usage. The backup EEPROM is invisible to the user and cannot be accessed by the user independently. Normal Device Operation The device includes circuitry that detects VCC dropping below a certain threshold, shuts its V (pin 8) System V CC CC connection to the outside environment, and transfers V Monitor CC all SRAM data to the EEPROM portion of each cell for safe keeping. When VCC returns, the circuitry V (pin 3) CAP automatically returns the data to the SRAM and the C Charged to V users interaction with the SRAM can continue with the VCAP CC CS same data set. Normal SO SRAM SI V (pin 4) Operation SS SCK Block Diagram HOLD System V VCC Power SS Control VCAP Block VCC Power-Off Event Memory Address and Data Control CS V (pin 8) SPI Control Logic System V Logic CC CC SO Automatic and Address SI Backup Decoder SCK V (pin 3) CAP HOLD EEPROM C EEPROM Temporary V VCAP CC SRAM STATUS CS 8K x 8 Register SO SRAM to V (pin 4) SS SI EEPROM SRAM SCK Transfer STORE HOLD 8K x 8 System V SS RECALL 2018-2019 Microchip Technology Inc. Preliminary DS20006055B-page 2