v3.0 HiRel FPGAs Features Low-Power 0.8 CMOS Technology Highly Predictable Performance with 100% Automatic 3200DX Features Placement and Routing 100 MHz System Logic Integration Device Sizes from 1,200 to 20,000 Gates Highest Speed FPGA SRAM, up to 2.5 kbits Configurable Up to 6 Fast, Low-Skew Clock Networks Dual-Port SRAM Up to 202 User-Programmable I/O Pins Fast Wide-Decode Circuitry More Than 500 Macro Functions Low-Power 0.6 CMOS Technology Up to 1,276 Dedicated Flip-Flops 1200XL Features I/O Drive to 10 mA Pin for Pin Compatible with ACT 2 Devices Available to DSCC SMD System Performance to 50 MHz over Military Temperature CQFP and CPGA Packaging Low-Power 0.6 CMOS Technology Nonvolatile, User Programmable Logic Fully Tested Prior to Shipment ACT 2 Features 100% Military Temperature Tested (55C to +125C) Best-Value, High-Capacity FPGA Family QML Certified Devices System Performance to 40 MHz over Military Temperature Proven Reliability Data Available Low-Power 1.0 CMOS Technology Successful Military/Avionics Supplier for Over 10 Years ACT 1 Features ACT 3 Features Lowest-Cost FPGA Family Highest-Performance, Highest-Capacity FPGA Family System Performance to 20 MHz over Military Temperature System Performance to 60 MHz over Military Temperature Low-Power 1.0 CMOS Technology Product Family Profile (more devices on page 2) Family 3200DX ACT 3 1200XL Device A32100DX A32200DX A1425A A1460A A14100A A1280XL Capacity System Gates 15,000 30,000 3,750 9,000 15,000 12,000 Logic Gates 10,000 20,000 2,500 6,000 10,000 8,000 SRAM Bits 2,048 2,560 NA NA NA Logic Modules 1,362 2,414 310 848 1,377 1,232 S-Modules 700 1,230 160 432 697 624 C-Modules 662 1,184 150 416 680 608 Decode 20 24 NA NA NA NA Flip-Flops (Maximum) 738 1,276 435 976 1,493 998 User I/Os (Maximum) 152 202 100 168 228 140 Performance System Speed (maximum) 55 MHz 55 MHz 60 MHz 60 MHz 60 MHz 50 MHz Packages (by Pin Count) CPGA 133 207 257 176 CQFP 84 208, 256 132 196 256 172 January 2000 1 2000 Actel CorporationProduct Family Profile Family ACT 2 ACT 1 Device A1240A A1280A A1010B A1020B Capacity System Gates 6,000 12,000 1,800 3,000 Logic Gates 4,000 8,000 1,200 2,000 SRAM Bits NA NA NA NA Logic Modules 684 1,232 295 547 S-Modules 348 624 C-Modules 336 608 295 547 Decode NA NA NA NA Flip-Flops (maximum) 568 998 147 273 User I/Os (maximum) 104 140 57 69 Packages (by pin count) CPGA 132 176 84 84 CQFP 172 84 Performance 20 MHz 20 MHz System Speed (maximum) 40 MHz 40 MHz High-Reliability, Low-Risk Solution junction temperatures. Actels non-PLD architecture delivers lower dynamic operating current. Our reliability tests show a Actel builds the most reliable field programmable gate arrays very low failure rate of 6.6 FITs at 90C junction temperature (FPGAs) in the industry, with overall antifuse reliability with no degradation in AC performance. Special stress testing ratings of less than 10 Failures-In-Time (FITs), at wafer test eliminates infant mortalities prior to packaging. corresponding to a useful life of more than 40 years. Actel FPGAs have been production proven, with more than five Minimized Security Risk million devices shipped and more than one trillion antifuses Reverse engineering of programmed Actel devices from manufactured. Actel devices are fully tested prior to optical or electrical data is extremely difficult. Programmed shipment, with an outgoing defect level of less than 100 ppm. antifuses cannot be identified from a photograph or by using (Further reliability data is available in the Actel Device an SEM. The antifuse map cannot be deciphered either Reliability Report, at