A3P250-FGG256I Microchip

Revision 18 DS0097 ProASIC3 Flash Family FPGAs with Optional Soft ARM Support Advanced I/O Features and Benefits 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above) High Capacity 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation 15 K to 1 M System Gates Wide Range Power Supply Voltage Support per JESD8-B, Up to 144 Kbits of True Dual-Port SRAM Allowing I/Os to Operate from 2.7 V to 3.6 V Up to 300 User I/Os Bank-Selectable I/O Voltagesup to 4 Banks per Chip Single-Ended I/O Standards: LVTTL, LVCMOS 3.3V/ Reprogrammable Flash Technology 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X and LVCMOS 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS 2.5 V / 5.0 V Input Process Differential I/O Standards: LVPECL, LVDS, B-LVDS, and Instant On Level 0 Support M-LVDS (A3P250 and above) Single-Chip Solution I/O Registers on Input, Output, and Enable Paths Retains Programmed Design when Powered Off Hot-Swappable and Cold Sparing I/Os High Performance Programmable Output Slew Rate and Drive Strength 350 MHz System Performance Weak Pull-Up/-Down 3.3 V, 66 MHz 64-Bit PCI IEEE 1149.1 (JTAG) Boundary Scan Test In-System Programming (ISP) and Security Pin-Compatible Packages across the ProASIC3 Family ISP Using On-Chip 128-Bit Advanced Encryption Standard Clock Conditioning Circuit (CCC) and PLL (AES) Decryption (except ARM -enabled ProASIC 3 devices) Six CCC Blocks, One with an Integrated PLL via JTAG (IEEE 1532compliant) Configurable Phase-Shift, Multiply/Divide, Delay Capabilities FlashLock to Secure FPGA Contents and External Feedback Low Power Wide Input Frequency Range (1.5 MHz to 350 MHz) Core Voltage for Low Power Embedded Memory Support for 1.5 V-Only Systems 1 Kbit of FlashROM User Nonvolatile Memory Low-Impedance Flash Switches SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM High-Performance Routing Hierarchy Blocks (1, 2, 4, 9, and 18 organizations) Segmented, Hierarchical Routing and Clock Structure True Dual-Port SRAM (except 18) ARM Processor Support in ProASIC3 FPGAs M1 ProASIC3 DevicesARM Cortex -M1 Soft Processor Available with or without Debug 1 ProASIC3 Devices A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000 2 Cortex-M1 Devices M1A3P250 M1A3P400 M1A3P600 M1A3P1000 System Gates 15,000 30,000 60,000 125,000 250,000 400,000 600,000 1,000,000 Typical Equivalent Macrocells 128 256 512 1,024 2,048 VersaTiles (D-flip-flops) 384 768 1,536 3,072 6,144 9,216 13,824 24,576 RAM Kbits (1,024 bits) 18 36 36 54 108 144 4,608-Bit Blocks 4 8 8 12 24 32 FlashROM Kbits 11 1 1 1 1 1 1 3 Secure (AES) ISP Yes Yes Yes Yes Yes Yes Integrated PLL in CCCs 1 1 1 1 1 1 4 VersaNet Globals 6 6 18 18 18 18 18 18 I/O Banks 22 2 2 4 4 4 4 Maximum User I/Os 49 81 96 133 157 194 235 300 Notes: 1. A3P015 is not recommended for new designs. 2. Refer to the Cortex-M1 product brief for more information. 3. AES is not available for Cortex-M1 ProASIC3 devices. 4. Six chip (main) and three quadrant global networks are available for A3P060 and above. 5. The M1A3P250 device does not support this package. 6. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs datasheet. 7. Package not available. A3P015 and A3P030 devices do not support this feature. Supported only by A3P015 and A3P030 devices. March 2016 I 2016 Microsemi CorporationProASIC3 Flash Family FPGAs 1 ProASIC3 Devices A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000 2 Cortex-M1 Devices M1A3P250 M1A3P400 M1A3P600 M1A3P1000 Package Pins 7 7 7 QFN QN68 QN48, QN68, QN132 QN132 QN132 7 QN132 CS CS121 VQFP VQ100 VQ100 VQ100 VQ100 TQFP TQ144 TQ144 PQFP PQ208 PQ208 PQ208 PQ208 PQ208 5 FBGA FG144 FG144 FG144/256 FG144/256/ FG144/256/ FG144/256/ 484 484 484 Notes: 1. A3P015 is not recommended for new designs. 2. Refer to the Cortex-M1 product brief for more information. 3. AES is not available for Cortex-M1 ProASIC3 devices. 4. Six chip (main) and three quadrant global networks are available for A3P060 and above. 5. The M1A3P250 device does not support this package. 6. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs datasheet. 7. Package not available. II Revision 18