Revision 13 DS0111 ProASIC3 nano Flash FPGAs Advanced I/Os Features and Benefits 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Wide Range of Features Bank-Selectable I/O Voltagesup to 4 Banks per Chip 10 k to 250 k System Gates Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / Up to 36 kbits of True Dual-Port SRAM 2.5 V / 1.8 V / 1.5 V Up to 71 User I/Os Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V Reprogrammable Flash Technology I/O Registers on Input, Output, and Enable Paths 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Selectable Schmitt Trigger Inputs Process Hot-Swappable and Cold-Sparing I/Os Instant On Level 0 Support Programmable Output Slew Rate and Drive Strength Single-Chip Solution Weak Pull-Up/-Down Retains Programmed Design when Powered Off IEEE 1149.1 (JTAG) Boundary Scan Test High Performance Pin-Compatible Packages across the ProASIC3 Family 350 MHz System Performance Clock Conditioning Circuit (CCC) and PLL In-System Programming (ISP) and Security Up to Six CCC Blocks, One with an Integrated PLL ISP Using On-Chip 128-Bit Advanced Encryption Standard Configurable Phase Shift, Multiply/Divide, Delay (AES) Decryption via JTAG (IEEE 1532compliant) Capabilities and External Feedback Wide Input Frequency Range (1.5 MHz to 350 MHz) FlashLock Designed to Secure FPGA Contents Low Power Embedded Memory 1 kbit of FlashROM User Nonvolatile Memory Low Power ProASIC 3 nano Products SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM 1.5 V Core Voltage for Low Power Support for 1.5 V-Only Systems Blocks (1, 2, 4, 9, and 18 organizations) Low-Impedance Flash Switches True Dual-Port SRAM (except 18 organization) High-Performance Routing Hierarchy Enhanced Commercial Temperature Range Segmented, Hierarchical Routing and Clock Structure T = 20C to +85C j Table 1 ProASIC3 nano Devices ProASIC3 nano Devices A3PN010 A3PN020 A3PN060 A3PN125 A3PN250 System Gates 10,000 20,000 60,000 125,000 250,000 Typical Equivalent Macrocells 86 172 512 1,024 2,048 VersaTiles (D-flip-flops) 260 520 1,536 3,072 6,144 2 RAM Kbits (1,024 bits) 18 36 36 2 4,608-Bit Blocks 4 8 8 FlashROM Kbits 1 1 1 1 1 2 Secure (AES) ISP Yes Yes Yes 2 Integrated PLL in CCCs 1 1 1 VersaNet Globals 4 4 18 18 18 I/O Banks 2 3 2 2 4 Maximum User I/Os (packaged device) 34 49 71 71 68 Maximum User I/Os (Known Good Die) 34 52 71 71 68 Package Pins QFN QN48 QN68 VQ100 VQ100 VQ100 VQFP Notes: 1. For higher densities and support of additional features, refer to the DS0097: ProASIC3 Family Flash FPGAs Datasheet and DS0098: ProASIC3E Flash Family FPGAs Datasheet. A3PN030 and smaller devices do not support this feature. October 2019 I 2019 Microsemi CorporationI/Os Per Package ProASIC3 nano Devices A3PN010 A3PN020 A3PN060 A3PN125 A3PN250 Known Good Die 34 52 71 71 68 QN48 34 QN68 49 VQ100 71 71 68 Notes: 2. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 FPGA Fabric Users Guide to ensure compliance with design and board migration requirements. 3. indicates RoHS-compliant packages. Refer toProASIC3 nano Ordering Informatio on page III for the location of the in the part number. For nano devices, the VQ100 package is offered in both leaded and RoHS-compliant versions. All other packages are RoHS-compliant only. Table 2 ProASIC3 nano FPGAs Package Sizes Dimensions Packages QN48 QN68 VQ100 Length Width (mm mm) 6 x 6 8 x 8 14 x 14 Nominal Area (mm2) 36 64 196 Pitch (mm) 0.4 0.4 0.5 Height (mm) 0.90 0.90 1.20 ProASIC3 nano Device Status ProASIC3 nano Devices Status A3PN010 Production A3PN020 Production A3PN060 Production A3PN125 Production A3PN250 Production II Revision 13