Revision 11 40MX and 42MX FPGA Families HiRel Features Features Commercial, Industrial, Automotive, and Military High Capacity Temperature Plastic Packages Single-Chip ASIC Alternative Commercial, Military Temperature, and MIL-STD-883 3,000 to 54,000 System Gates Ceramic Packages Up to 2.5 kbits Configurable Dual-Port SRAM QML Certification Fast Wide-Decode Circuitry Ceramic Devices Available to DSCC SMD Up to 202 User-Programmable I/O Pins Ease of Integration Mixed-Voltage Operation (5.0V or 3.3V for core and High Performance I/Os), with PCI-Compliant I/Os 5.6 ns Clock-to-Out Up to 100% Resource Utilization and 100% Pin Locking 250 MHz Performance Deterministic, User-Controllable Timing 5 ns Dual-Port SRAM Access Unique In-System Diagnostic and Verification Capability 100 MHz FIFOs with Silicon Explorer II 7.5 ns 35-Bit Address Decode Low Power Consumption IEEE Standard 1149.1 (JTAG) Boundary Scan Testing Product Profile Device A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 Capacity System Gates 3,000 6,000 14,000 24,000 36,000 54,000 SRAM Bits 2,560 Logic Modules Sequential 348 624 954 1,230 Combinatorial 295 547 336 608 912 1,184 Decode 24 24 Clock-to-Out 9.5 ns 9.5 ns 5.6 ns 6.1 ns 6.1 ns 6.3 ns SRAM Modules (64x4 or 32x8) 10 Dedicated Flip-Flops 348 624 954 1,230 Maximum Flip-Flops 147 273 516 928 1,410 1,822 Clocks 11 2 2 2 6 User I/O (maximum) 57 69 104 140 176 202 PCI Yes Yes Boundary Scan Test (BST) Yes Yes Packages (by pin count) PLCC 44, 68 44, 68, 84 84 84 84 PQFP 100 100 100, 160 100, 160, 208 160, 208 208, 240 VQFP 80 80 100 100 TQFP 176 176 176 CQFP 208, 256 PBGA 272 May 2012 i 2012 Microsemi Corporation40MX and 42MX FPGA Families Ordering Information A42MX16 1 PQ G 100 ES Application (Temperature Range) Blank = Commercial (0 to +70C) I = Industrial (40 to +85C) M = Military (55 to +125C) B = MIL-STD-883 A = Automotive (40 to +125C) Package Lead Count Lead-Free Packaging Blank = Standard Packaging G = RoHS Compliant Packaging Package Type PL = Plastic Leaded Chip Carrier PQ = Plastic Quad Flat Pack TQ = Thin (1.4 mm) Quad Flat Pack VQ = Very Thin (1.0 mm) Quad Flat Pack BG = Plastic Ball Grid Array CQ =Ceramic Quad Flat Pack Speed Grade Blank = Standard Speed 1 = Approximately 15% Faster than Standard 2 = Approximately 25% Faster than Standard 3 = Approximately 35% Faster than Standard F = Approximately 40% Slower than Standard Part Number A40MX02 = 3,000 System Gates A40MX04 = 6,000 System Gates A42MX09 = 14,000 System Gates A42MX16 = 24,000 System Gates A42MX24 = 36,000 System Gates A42MX36 = 54,000 System Gates Plastic Device Resources User I/Os PLCC PLCC PLCC PQFP PQFP PQFP PQFP VQFP VQFP TQFP PBGA Device 44-Pin 68-Pin 84-Pin 100-Pin 160-Pin 208-Pin 240-Pin 80-Pin 100-Pin 176-Pin 272-Pin A40MX02 34 57 57 57 A40MX04 34 57 69 69 69 A42MX09 72 83 101 83 104 A42MX16 72 83 125 140 83 140 A42MX24 72 125 176 150 A42MX36 176 202 202 Note: Package Definitions PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack, PBGA = Plastic Ball Grid Array ii Revision 11