v5.3 SX-A Family FPGAs u e Configurable I/O Support for 3.3 V / 5 V PCI, 5 V Leading-Edge Performance TTL, 3.3 V LVTTL, 2.5 V LVCMOS2 250 MHz System Performance 2.5 V, 3.3 V, and 5 V Mixed-Voltage Operation with 350 MHz Internal Performance 5 V Input Tolerance and 5 V Drive Strength Devices Support Multiple Temperature Grades Configurable Weak-Resistor Pull-Up or Pull-Down Specifications for I/O at Power-Up Individual Output Slew Rate Control 12,000 to 108,000 Available System Gates Up to 100% Resource Utilization and 100% Pin Up to 360 User-Programmable I/O Pins Locking Up to 2,012 Dedicated Flip-Flops Deterministic, User-Controllable Timing 0.22 / 0.25 CMOS Process Technology Unique In-System Diagnostic and Verification Capability with Silicon Explorer II Features Boundary-Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) Hot-Swap Compliant I/Os Actel Secure Programming Technology with Power-Up/Down Friendly (No Sequencing Required FuseLock Prevents Reverse Engineering and for Supply Voltages) Design Theft 66 MHz PCI Compliant Nonvolatile, Single-Chip Solution Table 1 SX-A Product Profile Device A54SX08A A54SX16A A54SX32A A54SX72A Capacity Typical Gates 8,000 16,000 32,000 72,000 System Gates 12,000 24,000 48,000 108,000 Logic Modules 768 1,452 2,880 6,036 Combinatorial Cells 512 924 1,800 4,024 Dedicated Flip-Flops 256 528 1,080 2,012 1 Maximum Flip-Flops 512 990 1,980 4,024 Maximum User I/Os 130 180 249 360 Global Clocks 3 3 3 3 Quadrant Clocks 0 0 0 4 Boundary Scan Testing Yes Yes Yes Yes 3.3 V / 5 V PCI Yes Yes Yes Yes Input Set-Up (External) 0 ns 0 ns 0 ns 0 ns 2 Speed Grades F, Std, 1, 2 F, Std, 1, 2, 3 F, Std, 1, 2, 3 F, Std, 1, 2, 3 Temperature Grades C, I, A, M C, I, A, M C, I, A, M C, I, A, M Package (by pin count) PQFP 208 208 208 208 TQFP 100, 144 100, 144 100, 144, 176 PBGA 329 FBGA 144 144, 256 144, 256, 484 256, 484 CQFP 208, 256 208, 256 Notes: 1. A maximum of 512 registers is possible if all 512 C cells are used to build an additional 256 registers. 2. All 3 speed grades have been discontinued. February 2007 i 2007 Actel Corporation See the Actel website for the latest version of the datasheet.SX-A Family FPGAs Ordering Information A54SX16A 2 PQ 208 G Application (Temperature Range) Blank = Commercial (0 to +70) I = Industrial (-40 to +85C) A = Automotive (-40 to +125C) M = Military (-55 to +125C) B = MIL-STD-883 Class B Package Lead Count Lead-Free Packaging Blank = Standard Packaging G = RoHS Compliant Packaging Package Type BG = 1.27 mm Plastic Ball Grid Array FG = 1.0 mm Fine Pitch Ball Grid Array PQ = Plastic Quad Flat Pack TQ = Thin (1.4 mm) Quad Flat Pack 1 CQ = Ceramic Quad Flat Pack Speed Grade Blank = Standard Speed 1 = Approximately 15% Faster than Standard 2 = Approximately 25% Faster than Standard 2 3 = Approximately 35% Faster than Standard F = Approximately 40% Slower than Standard Part Number A54SX08A = 12,000 System Gates A54SX16A = 24,000 System Gates A54SX32A = 48,000 System Gates A54SX72A = 108,000 System Gates Notes: 1. For more information about the CQFP package options, refer to the HiRel SX-A datasheet. 2. All 3 speed grades have been discontinued. Device Resources User I/Os (Including Clock Buffers) 208-Pin 100-Pin 144-Pin 176-Pin 329-Pin 144-Pin 256-Pin 484-Pin Device PQFP TQFP TQFP TQFP PBGA FBGA FBGA FBGA A54SX08A 130 81 113 111 A54SX16A 175 81 113 111 180 A54SX32A 174 81 113 147 249 111 203 249 A54SX72A 171 203 360 Notes: Package Definitions: PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch Ball Grid Array ii v5.3