v2.0 HiRel SX-A Family FPGAs Actel Secure Programming Technology with Features and Benefits FuseLock Prevents Reverse Engineering and Design Theft Leading Edge Performance Cold-Sparing Capability Individual Output Slew Rate Control 215 MHz System Performance (Military Temperature) QML Certified Devices 5.3 ns Clock-to-Out (Pin-to-Pin) (Military Temperature) 100% Military Temperature Tested (55C to +125C) 240 MHz Internal Performance (Military Temperature) 33 MHz PCI Compliant CPLD and FPGA Integration Specifications Single-Chip Solution 48,000 to 108,000 Available System Gates Configurable I/O Support for 3.3 V/5 V PCI, LVTTL, Up to 228 User-Programmable I/O Pins and TTL Up to 2,012 Dedicated Flip-Flops Configurable Weak Resistor Pull-Up or Pull-Down for 0.25/0.22 CMOS Process Technology Tristated Outputs during Power-Up Up to 100% Resource Utilization and 100% Pin Locking Features 2.5 V, 3.3 V, and 5 V Mixed Voltage Operation with Hot-Swap Compliant I/Os 5 V Input Tolerance and 5 V Drive Strength Power-Up/Down Friendly (no sequencing required Very Low Power Consumption for supply voltages) Deterministic, User-Controllable Timing Class B Level Devices Unique In-System Diagnostic and Verification Three Standard Hermetic Package Options Capability with Silicon Explorer II Boundary-Scan Testing in Compliance with IEEE 1149.1 (JTAG) Product Profile Device A54SX32A A54SX72A Capacity Typical Gates 32,000 72,000 System Gates 48,000 108,000 Logic Modules 2,880 6,036 Combinatorial Cells 1,800 4,024 Register Cells Dedicated Flip-Flops 1,080 2,012 Maximum Flip-Flops 1,980 4,024 Maximum User I/Os 228 213 Global Clocks 33 Quadrant Clocks 04 Boundary-Scan Testing Yes Yes 3.3 V / 5 V PCI Yes Yes Clock-to-Out 5.3 ns 6.7 ns Input Set-Up (External) 0 ns 0 ns Speed Grades Std, 1 Std, 1 Package (by Pin Count) CQFP 84, 208, 256 208, 256 November 2006 i 2006 Actel Corporation See the Actel website for the latest version of the datasheet.HiRel SX-A Family FPGAs Ordering Information A54SX32A 1 CQ 208 M Application (Ambient Temperature Range) M = Military (55 to +125C) B = MIL-STD-883 Class B Package Lead Count Package Type CQ = Ceramic Quad Flat Pack Speed Grade Blank = Standard Speed 1 = Approximately 15% Faster than Standard Part Number A54SX32A = 48,000 System Gates A54SX72A = 108,000 System Gates Figure 1 HiRel SX-A Family Ordering Information Ceramic Device Resources User I/Os (including clock buffers) Device CQFP 84-Pin CQFP 208-Pin CQFP 256-Pin A54SX32A 62 174 228 A54SX72A 171 213 Note: Package Definitions: CQFP = Ceramic Quad Flat Pack ii v2.0