Revision 23
IGLOO Low Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Bank-Selectable I/O Voltagesup to 4 Banks per Chip
Low Power
Single-Ended I/O Standards: LVTTL, LVCMOS
1.2 V to 1.5 V Core Voltage Support for Low Power
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X ,
Supports Single-Voltage System Operation
and LVCMOS 2.5 V / 5.0 V Input
5 W Power Consumption in Flash*Freeze Mode
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-
Low Power Active FPGA Operation
LVDS (AGL250 and above)
Flash*Freeze Technology Enables Ultra-Low Power
Wide Range Power Supply Voltage Support per JESD8-B,
Consumption while Maintaining FPGA Content
Allowing I/Os to Operate from 2.7 V to 3.6 V
Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode
Wide Range Power Supply Voltage Support per JESD8-12,
High Capacity
Allowing I/Os to Operate from 1.14 V to 1.575 V
15K to 1 Million System Gates I/O Registers on Input, Output, and Enable Paths
Up to 144 Kbits of True Dual-Port SRAM Hot-Swappable and Cold-Sparing I/Os
Up to 300 User I/Os Programmable Output Slew Rate and Drive Strength
Weak Pull-Up/-Down
Reprogrammable Flash Technology
IEEE 1149.1 (JTAG) Boundary Scan Test
130-nm, 7-Layer Metal, Flash-Based CMOS Process
Pin-Compatible Packages across the IGLOO Family
Instant On Level 0 Support
Clock Conditioning Circuit (CCC) and PLL
Single-Chip Solution
Retains Programmed Design When Powered Off Six CCC Blocks, One with an Integrated PLL
250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Configurable Phase Shift, Multiply/Divide, Delay Capabilities,
Performance and External Feedback
Wide Input Frequency Range (1.5 MHz up to 250 MHz)
In-System Programming (ISP) and Security
Embedded Memory
ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption (except ARM -enabled IGLOO devices) via 1 kbit of FlashROM User Nonvolatile Memory
JTAG (IEEE 1532compliant) SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
FlashLock Designed to Secure FPGA Contents Blocks (1, 2, 4, 9, and 18 organizations)
True Dual-Port SRAM (except 18)
High-Performance Routing Hierarchy
ARM Processor Support in IGLOO FPGAs
Segmented, Hierarchical Routing and Clock Structure
M1 IGLOO DevicesCortex-M1 Soft Processor Available
Advanced I/O
with or without Debug
700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)
1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
1
IGLOO Devices AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000
2
ARM-Enabled IGLOO Devices M1AGL250 M1AGL600 M1AGL1000
System Gates 15,000 30,000 60,000 125,000 250,000 400,000 600,000 1,000,000
Typical Equivalent Macrocells 128 256 512 1,024 2,048
VersaTiles (D-flip-flops) 384 768 1,536 3,072 6,144 9,216 13,824 24,576
Flash*Freeze Mode (typical, W) 5 5 10 16 24 32 36 53
RAM kbits (1,024 bits) 18 36 36 54 108 144
4,608-Bit Blocks 4 8 8 12 24 32
FlashROM Kbits (1,024 bits) 1 1 1 1 1 1 1 1
2
AES-Protected ISP Yes Yes Yes Yes Yes Yes
3
Integrated PLL in CCCs 1 1 1 1 1 1
4
VersaNet Globals 6 6 18 18 18 18 18 18
I/O Banks 2 2 2 2 4 4 4 4
Maximum User I/Os 49 81 96 133 143 194 235 300
Package Pins
3 5
UC/CS UC81 CS121 CS196 CS81, CS196 CS196 CS281 CS281
CS81
5,6
QFN QN68 QN48, QN68, QN132 QN132 QN132
QN132 VQ100
VQFP VQ100 VQ100 FG144 VQ100
6
FBGA FG144 FG144 FG144, FG256, FG144, FG256, FG144, FG256,
FG484 FG484 FG484
Notes:
1. AGL015 is not recommended for new designs
2. AES is not available for ARM-enabled IGLOO devices.
3. AGL060 in CS121 does not support the PLL.
4. Six chip (main) and twelve quadrant global networks are available for AGL060 and above.
5. The M1AGL250 device does not support this package.
6. Device/package support TBD.
7. The IGLOOe datasheet and IGLOOe FPGA Fabric Users Guide provide information on higher densities and additional features.
AGL015 and AGL030 devices do not support this feature. Supported only by AGL015 and AGL030 devices.
December 2012 I
2012 Microsemi CorporationIGLOO Low Power Flash FPGAs
1
I/Os Per Package
2
IGLOO Devices AGL015 AGL030 AGL060 AGL125 AGL250 AGL600 AGL1000
AGL400
ARM-Enabled
IGLOO Devices M1AGL250 M1AGL600 M1AGL1000
3
I/O Type
Package
QN48 34
QN68 49 49
UC81 66
CS81 66 60 7
CS121 96 96
VQ100 77 71 71 68 13
5,6 5,6
QN132 81 80 84 87 19
5 5
CS196 133 143 35 143 35
7
FG144 96 97 97 24 97 25 97 25 97 25
7
FG256 178 38 177 43 177 44
CS281 215 53 215 53
7
FG484 194 38 235 60 300 74
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the IGLOO FPGA Fabric Users Guide to
ensure compliance with design and board migration requirements.
2. AGL015 is not recommended for new designs.
3. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-
ended user I/Os available is reduced by one.
4. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
5. The M1AGL250 device does not support QN132 or CS196 packages.
6. Device/package support TBD.
7. FG256 and FG484 are footprint-compatible packages.
Table 1 IGLOO FPGAs Package Sizes Dimensions
Package UC81 CS81 CS121 QN48 QN68 QN132 CS196 CS281 FG144 VQ100 FG256 FG484
Length Width 4 4 5 5 6 6 6 6 8 8 8 8 8 8 10 10 13 13 14 14 17 17 23 23
(mm\mm)
Nominal Area 16 25 36 36 64 64 64 100 169 196 289 529
2
(mm )
Pitch (mm) 0.4 0.5 0.5 0.4 0.4 0.5 0.5 0.5 1.0 0.5 1.0 1.0
Height (mm) 0.80 0.80 0.99 0.90 0.90 0.75 1.20 1.05 1.45 1.00 1.60 2.23
II Revision 23
Single-Ended I/O
Single-Ended I/O
Single-Ended I/O
Single-Ended I/O
4
Single-Ended I/O
Differential I/O Pairs
4
Single-Ended I/O
Differential I/O Pairs
4
Single-Ended I/O
Differential I/O Pairs
4
Single-Ended I/O
Differential I/O Pairs