Atmel AT27C040 4Mb (512K x 8) OTP, EPROM DATASHEET Features Fast read access time 70ns Low-power CMOS operation 100 A max standby 30mA max active at 5MHz JEDEC standard packages 32-lead PDIP 32-lead PLCC 5V 10% supply High-reliability CMOS technology 2000V ESD protection 200mA latchup immunity Rapid programming algorithm 100 s/byte (typical) CMOS- and TTL-compatible inputs and outputs Industrial temperature range Green (Pb/halide-free) packaging option 1. Description The Atmel AT27C040 is a low-power, high-performance, 4,194,304-bit, One-Time Programmable, Read-Only Memory (OTP EPROM) organized as 512K by 8 bits. The AT27C040 requires only one 5V power supply in normal Read mode operation. Any byte can be accessed in less than 70ns, eliminating the need for speed reducing wait states on high-performance microprocessor systems. The Atmel scaled CMOS technology provides low active power consumption and fast programming. Power consumption is typically 8mA in active mode and less than 10 A in standby mode. The AT27C040 is available in a choice of industry standard, JEDEC-approved, PDIP and PLCC packages. The device features two-line control (CE, OE) to eliminate bus contention in high-speed systems. The AT27C040 has additional features to ensure high quality and efficient production use. The rapid programming algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 100 s/byte. The integrated product identification code electronically identifies the device and manufacturer. This feature is used by industry standard programming equipment to select the proper programming algorithms and voltages. 0189JEPROM10/20122. Pin Configurations and Pinouts 32-lead PDIP 32-lead PLCC Pin Top view Top view Name Function V Peak to Peak Voltage PP V 1 32 V PP CC A - A Address Inputs 0 18 A 2 31 A 16 18 A 3 30 A O - O Outputs 15 17 0 7 A 5 29 A 7 14 A 4 29 A 12 14 A 6 28 A 6 13 GND Ground A 5 28 A 7 13 A 7 27 A 5 8 CE Chip Enable A 6 27 A 6 8 A 8 26 A 4 9 OE Output Enable A 7 26 A 5 9 A 9 25 A 3 11 A 8 25 A 4 11 A 10 24 OE V Device Power Supply 2 CC A 9 24 OE 3 A 11 23 A 1 10 A 10 23 A 2 10 A 12 22 CE 0 A 11 22 CE 1 O 13 21 O 0 7 A 12 21 O 0 7 O 13 20 O 0 6 O 14 19 O 1 5 O 15 18 O 2 4 GND 16 17 O 3 3. Switching Considerations Switching between active and standby conditions via the Chip Enable (CE) pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device nonconformance. At a minimum, a 0.1 F, high-frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the V and ground terminals of the device as CC close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7F bulk electrolytic capacitor should be utilized, again connected between the V and ground CC terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array. 4. Block Diagram V Data Outputs CC O O 0 7 GND V PP OE OE, CE, and Output Program Logic Buffers CE Y Decoder Y-Gating A A 0 18 Address Cell Matrix Inputs X Decoder Identification Atmel AT27C040 DATASHEET 2 0189JEPROM10/2012 O 14 4 A 1 12 O 15 3 A 2 15 GND 16 2 A 16 O 17 1 V 3 PP O 18 32 V 4 CC O 19 31 A 5 18 O 20 30 A 6 17