AT28C64B-15SU-T Microchip

Features Fast Read Access Time 150 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Fast Write Cycle Times Page Write Cycle Time: 10 ms Maximum (Standard) 2 ms Maximum (Option Ref. AT28HC64BF Datasheet) 1 to 64-byte Page Write Operation Low Power Dissipation 64K (8K x 8) 40 mA Active Current 100 A CMOS Standby Current Parallel Hardware and Software Data Protection DATA Polling and Toggle Bit for End of Write Detection EEPROM with High Reliability CMOS Technology Endurance: 100,000 Cycles Page Write and Data Retention: 10 Years Single 5V 10% Supply Software Data CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-wide Pinout Protection Industrial Temperature Ranges Green (Pb/Halide-free) Packaging Option Only AT28C64B 1. Description The AT28C64B is a high-performance electrically-erasable and programmable read- only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits. Manufactured with Atmels advanced nonvolatile CMOS technology, the device offers access times to 150 ns with power dissipation of just 220 mW. When the device is deselected, the CMOS standby current is less than 100 A. The AT28C64B is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA POLLING of I/O7. Once the end of a write cycle has been detected, a new access for a read or write can begin. Atmels AT28C64B has additional features to ensure high quality and manufacturabil- ity. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking. 0270LPEEPR2/092.2 32-lead PLCC Top View 2. Pin Configurations Pin Name Function A0 - A12 Addresses CE Chip Enable A6 5 29 A8 OE Output Enable A5 6 28 A9 A4 7 27 A11 Write Enable WE A3 8 26 NC I/O0 - I/O7 Data Inputs/Outputs A2 9 25 OE NC No Connect A1 10 24 A10 A0 11 23 CE DC Dont Connect NC 12 22 I/O7 I/O0 13 21 I/O6 Note: PLCC package pins 1 and 17 are Dont Connect. 2.1 28-lead PDIP, 28-lead SOIC Top View 2.3 28-lead TSOP Top View OE 1 28 A10 NC 1 28 VCC A11 2 27 CE A12 2 27 WE A9 3 26 I/O7 A7 3 26 NC A8 4 25 I/O6 A6 4 25 A8 NC 5 24 I/O5 A5 5 24 A9 WE 6 23 I/O4 A4 6 23 A11 VCC 7 22 I/O3 A3 7 22 OE NC 8 21 GND A2 8 21 A10 A12 9 20 I/O2 A1 9 20 CE A7 10 19 I/O1 A0 10 19 I/O7 A6 11 18 I/O0 I/O0 11 18 I/O6 A5 12 17 A0 I/O1 12 17 I/O5 A4 13 16 A1 I/O2 13 16 I/O4 A3 14 15 A2 GND 14 15 I/O3 2 AT28C64B 0270LPEEPR2/09 I/O1 14 4 A7 I/O2 15 3 A12 GND 16 2 NC DC 17 1 DC I/O3 18 32 VCC I/O4 19 31 WE I/O5 20 30 NC