AT28HC64B-70SU-T Microchip

Features Fast Read Access Time 70 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Fast Write Cycle Times Page Write Cycle Time: 10 ms Maximum (Standard) 2 ms Maximum (Option Ref. AT28HC64BF Datasheet) 1 to 64-byte Page Write Operation Low Power Dissipation 64K (8K x 8) 40 mA Active Current 100 A CMOS Standby Current High-speed Hardware and Software Data Protection DATA Polling and Toggle Bit for End of Write Detection Parallel High Reliability CMOS Technology Endurance: 100,000 Cycles EEPROM with Data Retention: 10 Years Single 5 V 10% Supply Page Write and CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-wide Pinout Software Data Industrial Temperature Ranges Green (Pb/Halide-free) Packaging Option Only Protection 1. Description AT28HC64B The AT28HC64B is a high-performance electrically-erasable and programmable read- only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits. Manufactured with Atmels advanced nonvolatile CMOS technology, the device offers access times to 55 ns with power dissipation of just 220 mW. When the device is deselected, the CMOS standby current is less than 100 A. The AT28HC64B is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected, a new access for a read or write can begin. Atmels AT28HC64B has additional features to ensure high quality and manufactura- bility. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mecha- nism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking. 0274LPEEPR2/3/092.2 32-lead PLCC Top View 2. Pin Configurations Pin Name Function A0 - A12 Addresses A6 5 29 A8 CE Chip Enable A5 6 28 A9 A4 7 27 A11 OE Output Enable A3 8 26 NC Write Enable WE A2 9 25 OE A1 10 24 A10 I/O0 - I/O7 Data Inputs/Outputs A0 11 23 CE NC 12 22 I/O7 NC No Connect I/O0 13 21 I/O6 DC Dont Connect Note: PLCC package pins 1 and 17 are Dont Connect. 2.1 28-lead SOIC Top View 2.3 28-lead TSOP Top View NC 1 28 VCC OE 1 28 A10 A12 2 27 WE A11 2 27 CE A7 3 26 NC A9 3 26 I/O7 A6 4 25 A8 A8 4 25 I/O6 A5 5 24 A9 NC 5 24 I/O5 A4 6 23 A11 WE 6 23 I/O4 A3 7 22 OE VCC 7 22 I/O3 A2 8 21 A10 NC 8 21 GND A1 9 20 CE A12 9 20 I/O2 A0 10 19 I/O7 A7 10 19 I/O1 I/O0 11 18 I/O6 A6 11 18 I/O0 I/O1 12 17 I/O5 A5 12 17 A0 I/O2 13 16 I/O4 A4 13 16 A1 GND 14 15 I/O3 A3 14 15 A2 2 AT28HC64B 0274LPEEPR2/3/09 I/O1 14 4 A7 I/O2 15 3 A12 GND 16 2 NC DC 17 1 DC I/O3 18 32 VCC I/O4 19 31 WE I/O5 20 30 NC