AT91SAM ARM-based Embedded MPU SAM9260 Features 180 MHz ARM926EJ-S ARM Thumb Processor 8 KBytes Data Cache, 8 KBytes Instruction Cache, MMU Memories 32-bit External Bus Interface supporting 4-bank SDRAM/LPSDR, Static Memories, CompactFlash, SLC NAND Flash with ECC Two 4-kbyte internal SRAM, single-cycle access at system speed One 32-kbyte internal ROM, embedding bootstrap routine Peripherals ITU-R BT. 601/656 Image Sensor Interface USB Device and USB Host with dedicated On-Chip Transceiver 10/100 Mbps Ethernet MAC Controller One High Speed Memory Card Host Two Master/Slave Serial Peripheral Interfaces Two Three-channel 32-bit Timer/Counters One Synchronous Serial Controller One Two-wire Interface Four USARTs Two UARTs 4-channel 10-bit ADC System 90 MHz six 32-bit layer AHB Bus Matrix 22 Peripheral DMA Channels Boot from NAND Flash, DataFlash or serial DataFlash Reset Controller with On-Chip Power-on Reset Selectable 32,768 Hz Low-Power and 3-20 MHz Main Oscillator Internal Low-Power 32 kHz RC Oscillator One PLL for the system and one PLL optimized for USB Two Programmable External Clock Signals Advanced Interrupt Controller and Debug Unit Periodic Interval Timer, Watchdog Timer and Real Time Timer I/O Three 32-bit Parallel Input/Output Controllers 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os Package 217-ball BGA, 0.8 mm pitch 208-pin QFP, 0.5 mm pitch This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 6221LSATARM15-Oct-12 1. Description The SAM9260 is based on the integration of an ARM926EJ-S processor with fast ROM and RAM memories and a wide range of peripherals. The SAM9260 embeds an Ethernet MAC, one USB Device Port, and a USB Host controller. It also integrates several standard peripherals, such as the USART, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and MultiMedia Card Interface. The SAM9260 is architectured on a 6-layer matrix, allowing a maximum internal bandwidth of six 32-bit buses. It also features an External Bus Interface capable of interfacing with a wide range of memory devices. 2. SAM9260 Block Diagram The block diagram shows all the features for the 217-LFBGA package. Some functions are not accessible in the 208-pin PQFP package and the unavailable pins are highlighted in Multiplexing on PIO Controller A on page 31, Multiplexing on PIO Controller B on page 32, Multiplexing on PIO Controller C on page 33. The USB Host Port B is not available in the 208-pin package. Table 2-1 on page 2 defines all the multiplexed and not multiplexed pins not available in the 208- PQFP package. Table 2-1. Unavailable Signals in 208-lead PQFP Package PIO Peripheral A Peripheral B - HDPB - - HDMB - PA30 SCK2 RXD4 PA31 SCK0 TXD4 PB12 TXD5 ISI D10 PB13 RXD5 ISI D11 PC2 AD2 PCK1 PC3 AD3 SPI1 NPCS3 PC12 IRQ0 NCS7 SAM9260 SUMMARY 2 6221LSATARM15-Oct-12