SAM9G25 Atmel SMART ARM-based Embedded MPU DATASHEET Description The SAM9G25 is a member of the Atmel SMART series of 400 MHz ARM926EJ-S embedded microprocessor units. This MPU features connectivity peripherals, a high data bandwidth architecture and a small footprint package option, making it an optimized solution for industrial applications. The SAM9G25 interface peripherals include a camera interface that supports direct connection to the ITU-R BT. 601/656 8-bit mode compliant sensors and up to 12-bit grayscale sensors. Communication peripherals include a soft modem supporting exclusively the Conexant SmartDAA line driver, HS (480 Mbps) USB Host and Device ports with on-chip transceivers, FS USB Host, 10/100 Ethernet MAC, two HS SDCard/SDIO/MMC interfaces, USARTs, SPIs, I2S, multiple TWIs and 10-bit ADC. The multi-layer bus matrix is linked to 2 x 8 DMA channels as well as DMAs dedicated to the communication and interface peripherals, ensuring uninterrupted data transfers with minimal processor overhead. The External Bus Interface incorporates controllers for 4-bank and 8-bank DDR2/LPDDR, SDRAM/LPSDRAM, static memories, as well as specific circuitry for MLC/SLC NAND Flash with integrated ECC up to 24 bits. The SAM9G25 is available in a 217-ball BGA package with 0.8 mm ball pitch, as well as in 247-ball TFBGA and 247-ball VFBGA packages with 0.5 mm ball pitch, making it ideally suited for space-constrained applications. Atmel-11032G-ATARM-SAM9G25-Datasheet 31-Aug-15Features Core ARM926EJ-S ARM Thumb Processor running at up to 400 MHz 1.0V +/- 10% 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit Memories One 64-Kbyte internal ROM embedding bootstrap routine: Boot on NAND Flash, SDCard, DataFlash or serial DataFlash. Programmable order. One 32-Kbyte internal SRAM, single-cycle access at system speed High Bandwidth Multi-port DDR SDR SDRAM Controller (DDRSDRC) 32-bit External Bus Interface supporting 4-bank and 8-bank DDR2/LPDDR, SDR/LPSDR, Static Memories MLC/SLC 8-bit NAND Controller, with up to 24-bit Programmable Multi-bit Error Correcting Code (PMECC) System running at up to 133 MHz Power-on Reset Cells, Reset Controller, Shutdown Controller, Periodic Interval Timer, Watchdog Timer and Real Time Clock Boot Mode Select Option, Remap Command Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator One PLL for the system and one PLL at 480 MHz optimized for USB High Speed Twelve 32-bit-layer AHB Bus Matrix for large Bandwidth transfers Dual Peripheral Bridge with dedicated programmable clock for best performances Two dual port 8-channel DMA Controllers (DMAC) Advanced Interrupt Controller (AIC) and Debug Unit (DBGU) Two Programmable External Clock Signals Low Power Mode Shutdown Controller with four 32-bit Battery Backup Registers Clock Generator and Power Management Controller Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities Peripherals ITU-R BT. 601/656 Image Sensor Interface (ISI) USB Device High Speed, USB Host High Speed and USB Host Full Speed with dedicated On-Chip Transceiver One 10/100 Mbps Ethernet MAC Controller (EMAC) Two High Speed Memory Card Hosts Two Master/Slave Serial Peripheral Interfaces (SPI) Two 3-channel 32-bit Timer/Counters (TC) One Synchronous Serial Controller (SSC) One 4-channel 16-bit PWM Controller 3 Two-wire Interfaces (TWI) Four USARTs, two UARTs, one DBGU One 12-channel 10-bit Analog-to-Digital Converter Software Modem Device (SMD) Write Protected Registers I/O Four 32-bit Parallel Input/Output Controllers 105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os Input Change Interrupt Capability on Each I/O Line, optional Schmitt trigger input Individually Programmable Open-drain, Pull-up and pull-down resistor, Synchronous Output 2 SAM9G25 DATASHEET Atmel-11032G-ATARM-SAM9G25-Datasheet 31-Aug-15