Features Monolithic Field Programmable System Level Integrated Circuit (FPSLIC ) AT40K SRAM-based FPGA with Embedded High-performance RISC AVR Core, Extensive Data and Instruction SRAM and JTAG ICE 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM High-performance DSP Optimized FPGA Core Cell Dynamically Reconfigurable In-System FPGA Configuration Access Available On-chip from AVR Microcontroller Core to Support Cache Logic Designs Very Low Static and Dynamic Power Consumption Ideal for Portable and Handheld Applications Patented AVR Enhanced RISC Architecture 5K - 40K Gates 120+ Powerful Instructions Most Single Clock Cycle Execution High-performance Hardware Multiplier for DSP-based Systems of AT40K FPGA Approaching 1 MIPS per MHz Performance C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers with 8-bit Low-power Idle, Power-save and Power-down Modes 100 A Standby and Typical 2-3 mA per MHz Active Microcontroller, Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM up to 36K Bytes Up to 16 Kbytes x 8 Internal 15 ns Data SRAM JTAG (IEEE std. 1149.1 Compliant) Interface of SRAM and Extensive On-chip Debug Support Limited Boundary-scan Capabilities According to the JTAG Standard (AVR Ports) On-chip AVR Fixed Peripherals Industry-standard 2-wire Serial Interface JTAG ICE Two Programmable Serial UARTs Two 8-bit Timer/Counters with Separate Prescaler and PWM One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture Modes and Dual 8-, 9- or 10-bit PWM AT94KAL Series Support for FPGA Custom Peripherals Field AVR Peripheral Control 16 Decoded AVR Address Lines Directly Accessible to FPGA Programmable FPGA Macro Library of Custom Peripherals 16 FPGA Supplied Internal Interrupts to AVR System Level Up to Four External Interrupts to AVR 8 Global FPGA Clocks Integrated Two FPGA Clocks Driven from AVR Logic FPGA Global Clock Access Available from FPGA Core Circuit Multiple Oscillator Circuits Programmable Watchdog Timer with On-chip Oscillator Oscillator to AVR Internal Clock Circuit Software-selectable Clock Frequency Oscillator to Timer/Counter for Real-time Clock V : 3.0V - 3.6V CC 3.3V 33 MHz PCI-compliant FPGA I/O 20 mA Sink/Source High-performance I/O Structures All FPGA I/O Individually Programmable High-performance, Low-power 0.35 CMOS Five-layer Metal Process State-of-the-art Integrated PC-based Software Suite including Co-verification 5V I/O Tolerant Green (Pb/Halide-free/ROHS compliant) Package Options Available 1138IFPSLI1/081. Description The AT94KAL Series FPSLIC family shown in Table 1-1 is a combination of the popular Atmel AT40K Series SRAM FPGAs and the high-performance Atmel AVR 8-bit RISC microcontroller with standard peripherals. Extensive data and instruction SRAM as well as device control and management logic are included on this monolithic device, fabricated on Atmels 0.35 five-layer metal CMOS process. The AT40K FPGA core is a fully 3.3V PCI-compliant, SRAM-based FPGA with distributed 10 ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks, Cache Logic ability (partially or fully reconfigurable without loss of data) and 5,000 to 40,000 usable gates. Table 1-1. The AT94K Series Characteristics Device AT94K05AL AT94K10AL AT94K40AL FPGA Gates 5K 10K 40K FPGA Core Cells 256 576 2304 FPGA SRAM Bits 2048 4096 18432 FPGA Registers (Total) 436 846 2862 Maximum FPGA User I/O 96 116 120 AVR Programmable I/O 816 16 Lines 20 Kbytes - 32 20 Kbytes - 32 Program SRAM 4 Kbytes - 16 Kbytes Kbytes Kbytes Data SRAM 4 Kbytes - 16 Kbytes 4 Kbytes- 16 Kbytes 4 Kbytes - 16 Kbytes Hardware Multiplier (8-bit) Yes Yes Yes 2-wire Serial Interface Yes Yes Yes UARTs 2 2 2 Watchdog Timer Yes Yes Yes Timer/Counters 3 3 3 Real-time Clock Yes Yes Yes (1) (1) (1) Yes Yes JTAG ICE Yes Typical AVR 25 19 MIPS 19 MIPS 19 MIPS throughput MHz Operating Voltage 3.0 - 3.6V 3.0 - 3.6V 3.0 - 3.6V Notes: 1. FPSLIC parts with JTAG ICE support can be identified by the letter J after the device date code, e.g., 4201 (no ICE support) and 4201J (with ICE support), see Figure 1-1. 2 AT94KAL Series FPSLIC 1138IFPSLI1/08