ATA664151 LIN System Basis Chip with LIN Transceiver, 5V Regulator, Watchdog, 8-channel High Voltage Switch Interface with High Voltage Current Sources, 16-bit SPI DATASHEET Features 8-channel HV switch interface with HV current sources Linear low-drop voltage regulator, up to 80mA current capability, V = 5.0V 2% CC Fulfills the OEM Hardware Requirements for LIN in Automotive Applications Rev.1.3 LIN master and slave operation possible Supply voltage up to 40V Operating voltage V = 5V to 27V S Internal voltage divider for V sensing (2%) Battery 16-bit serial interface (daisy-chain-capable) for configuration and diagnosis Typically 8A supply current during sleep mode Typically 35A supply current in active low-power mode VCC-undervoltage detection (4ms reset time) and watchdog reset logical combined at NRES open drain output LIN high-speed mode up to 200kBit/s Adjustable watchdog timer via external resistor Negative trigger input for watchdog LIN physical layer complies with LIN 2.1 specification and SAE J2602-2 Wake-up capability via LIN bus and CL15 Bus pin is overtemperature and short-circuit protected versus GND and battery Advanced EMC and ESD performance Package: QFN32 5x5mm 9268I-AUTO-04/151. Description The Atmel ATA664151 is a system basis chip with an eight-channel high voltage switch interface, a LIN 2.1 and SAEJ2602-2-compliant LIN transceiver, low-drop voltage regulator, and an adjustable window watchdog. The Atmel ATA664151 provides 5V output voltage with up to 80mA current capability. This chip combination makes it possible to develop inexpensive, simple, yet powerful slave and master nodes for LIN bus systems. The Atmel ATA664151 is especially designed for LIN switch applications and includes almost the entire LIN node. They are designed to handle low data-rate communication in vehicles (such as in convenience electronics). Improved slope control at the LIN driver ensures secure data communication up to 20kBaud. Sleep Mode and Active Low-power Mode guarantee minimal current consumption even in the case of a floating bus line or a short circuit on the LIN bus to GND. Figure 1-1. Block Diagram RXD TXD LIN VS NCS 16-bit Serial SCK Programming LIN Physical Layer Internal Voltage VCC Interface Interface Supplies Regulator MOSI (SPI) MISO VBATT CL15 HV Input VBATT Control Logic NIRQ VDIV Voltage Int. Oscillator Divider HV Switch PWM1 Window Watchdog Interface NRES WD-Oscillator (8x) PWM2 PWM3 NTRIG WDOSC AGND GND IREF CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 2 ATA664151 DATASHEET 9268IAUTO04/15