ATF16V8C-5JX Microchip

Features Industry-standard architecture Emulates Many 20-pin PALs Low-cost, easy to use software tools High speed electrically-erasable programmable logic devices (EE PLD) 5ns maximum pin-to-pin delay Low power, 100A pin controlled power-down mode option CMOS and TTL compatible inputs and outputs I/O pin keeper circuits High Performance Advanced flash technology Electrically-erasable Reprogrammable 100% tested Programmable High reliability CMOS process Logic Devices 20 year data retention 100 erase/write cycles 2,000V ESD protection Atmel ATF16V8C 200mA latchup immunity Commercial and industrial temperature ranges Dual-in-line and surface mount packages in standard pinouts PCI compliant Green (ROHS compliant) package options available Description The Atmel ATF16V8C is a high performance EECMOS programmable logic device (PLD) that utilizes the Atmel proven electrically-erasable (EE) Flash memory technology. Offered options include speeds down to 5ns and a 100A pin-controlled power-down mode. All speed ranges are specified over the full 5V 10% range for industrial temperature ranges, and 5V 5% for commercial range 5V devices. The ATF16V8C incorporates a superset of the generic architectures, which allows direct replacement of the 16R8 family and most 20-pin combinatorial PLDs. Eight outputs are each allocated eight product terms. Three different modes of operation are configured auto- matically with software, and allow highly complex logic functions to be realized. The ATF16V8C can significantly reduce total system power, thereby enhancing system reli- ability and reducing power supply costs. When pin 4 is configured as the power-down control pin, supply current drops to less than 100A whenever the pin is high. If the power- down feature isn t required for a particular application, pin 4 may be used as a logic input. Also, the pin-keeper circuits eliminate the need for internal pull-up resistors along with their attendant power consumption. 0425HPLD3/11Figure 0-1. Block diagram Note: 1. Includes optional PD control pin Figure 0-2. Pin configurations Pin name Function CLK Clock I Logic inputs I/O Bidirectinoal buffers OE Output enable V +5V supply CC PD Power-down TSSOP DIP/SOIC PLCC Top view Top view Top view I/CLK 1 20 VCC I/CLK 1 20 VCC I1 2 19 I/O I1 2 19 I/O I2 3 18 I/O I2 3 18 I/O PD/I3 4 18 I/O PD/I3 4 17 I/O PD/I3 4 17 I/O I4 5 17 I/O I4 5 16 I/O I4 5 16 I/O I5 6 16 I/O I5 6 15 I/O I5 6 15 I/O I6 7 14 I/O I6 7 15 I/O I6 7 14 I/O I7 8 14 I/O I7 8 13 I/O I7 8 13 I/O I8 9 12 I/O I8 9 12 I/O GND 10 11 I9/OE GND 10 11 I9/OE 2 Atmel ATF16V8C 0425HPLD3/11 I8 9 3 I2 GND 10 2 I1 I9/OE 11 1 I/CLK I/O 12 20 VCC I/O 13 19 I/O