Features 3.0V to 5.5V Operating Range Advanced Low-voltage Electrically-erasable Programmable Logic Device User-controlled Power-down Pin Option Pin-controlled Standby Power (10A Typical) Well-suited for Battery Powered Systems 10ns Maximum Propagation Delay CMOS and TTL Compatible Inputs and Outputs Latch Feature Hold Inputs to Previous Logic States High-performance Advanced Electrically-erasable Technology Reprogrammable Electrically 100% Tested High-reliability CMOS Process Erasable 20 year Data Retention 100 Erase/Write Cycles Programmable 2,000V ESD Protection Logic Device 200mA Latchup Immunity Industrial Temperature Ranges Dual-in-line and Surface Mount Packages in Standard Pinouts Atmel ATF22LV10C Inputs are 5V Tolerant See separate datasheet for Atmel Green Package Options (Pb/Halide-free/RoHS Compliant) Available ATF22LV10C(Q)Z option Applcations include Glue logic for 3.3V systems, DMA Control, State Machine Control, Graphics processing 1. Description The Atmel ATF22LV10C is a high-performance CMOS (electrically erasable) pro- grammable logic device (PLD) that utilizes the Atmel proven electrically erasable Flash memory technology. Speeds down to 10ns and power dissipation as low as 10mA are offered. All speed ranges are specified over the 3.0V to 5.5V range for industrial and commercial temperature ranges. The ATF22LV10C provides a low-voltage and user controlled zero power CMOS PLD solution. A user-controlled power-down feature offers zero (10A typical) standby power. This feature allows the user to manage total system power to meet specific application requirements and enhance reliability, all without sacrificing speed. (The Atmel ATF22LV10CQZ provides edge-sensing zero standby power (3A typi- cal), as well as low voltage operation. See the ATF22LV10CQZ datasheet.) The ATF22LV10C is capable of operating at supply voltages down to 3.0V. When the power-down pin is active, the device is placed into a zero standby power-down mode. When the power-down pin is not used or active, the device operates in a full power low voltage mode. Pin keeper circuits on input and output pins hold pins to their pre- vious logic levels when idle, which eliminate static power consumed by pull-up resistors. The ATF22LV10C macrocell incorporates a variable product term architecture. Each output is allocated from 8 to 16 product terms which allows highly-complex logic func- tions to be realized. Two additional product terms are included to provide synchronous reset and asynchronous reset. These additional product terms are common to all ten registers and are automatically cleared upon power-up. Register preload simplifies testing. A security fuse prevents unauthorized copying of programmed fuse patterns. 0780MPLD7/10Figure 1-1. Block Diagram Figure 1-2. Pin Configurations Pin Configurations (All Pinouts Top View) Pin Name Function CLK Clock IN Logic Inputs I/O Bi-directional Buffers VCC (3V to 5.5V) Supply PD Programmable Power-down Figure 1-3. TSSOP Figure 1-4. DIP/SOIC CLK/IN 1 24 VCC CLK/IN 1 24 VCC IN 2 23 I/O IN 2 23 I/O IN 3 22 I/O IN 3 22 I/O IN/PD 4 21 I/O IN/PD 4 21 I/O IN 5 20 I/O IN 5 20 I/O IN 6 19 I/O IN 6 19 I/O IN 7 18 I/O IN 7 18 I/O IN 8 17 I/O IN 8 17 I/O IN 9 16 I/O IN 9 16 I/O IN 10 15 I/O IN 10 15 I/O IN 11 14 I/O IN 11 14 I/O GND 12 13 IN GND 12 13 IN Figure 1-5. PLCC IN/PD 5 25 I/O IN 6 24 I/O IN 7 23 I/O GND* GND* 8 22 IN 9 21 I/O IN 10 20 I/O IN 11 19 I/O Note: For PLCC, pins 1, 8, 15, and 22 can be left unconnected. For superior performance, connect VCC to pin 1 and GND to 8, 15, and 22 2 Atmel ATF22LV10C 0780MPLD7/10 IN 12 4 IN IN 13 3 IN GND 14 2 CLK/IN GND* 15 1 VCC* IN 16 28 VCC I/O 17 27 I/O I/O 18 26 I/O