Features 3.0V to 5.5V Operating Range Advanced, High-speed, Electrically-erasable Programmable Logic Device Superset of 22V10 Enhanced Logic Flexibility Architecturally Compatible with ATV750B and ATV750 Software and Hardware D- or T-type Flip-flop Product Term or Direct Input Pin Clocking 10 ns Maximum Pin-to-pin Delay with 5V Operation High-speed 15 ns Maximum Pin-to-pin Delay with 3V Operation Highest Density Programmable Logic Available in 24-pin Package Complex Advanced Electrically-erasable Technology Reprogrammable Programmable 100% Tested Increased Logic Flexibility Logic Device 42 Array Inputs, 20 Sum Terms and 20 Flip-flops Enhanced Output Logic Flexibility All 20 Flip-flops Feed Back Internally ATF750LVC 10 Flip-flops are also Available as Outputs Programmable Pin-keeper Circuits Dual-in-line and Surface Mount Package in Standard Pinouts Commercial and Industrial Temperature Ranges 20-year Data Retention 2000V ESD Protection 1000 Erase/Write Cycles Green Package Options (Pb/Halide-free/RoHS Compliant) Available 1. Block Diagram (OE PRODUCT TERMS) PROGRAMMABLE 12 LOGIC INTERCONNECT 4TO 8 10 INPUT OPTION AND OUTPUT PRODUCT I/O PINS COMBINATORIAL OPTION TERMS (UP T0 20 PINS LOGIC ARRAY FLIP-FLOPS) (CLOCK PIN) 2. Description The Atmel 750 architecture is twice as powerful as most other 24-pin programma- ble logic devices. Increased product terms, sum terms, flip-flops and output logic configurations translate into more usable gates. High-speed logic and uniform, pre- dictable delays guarantee fast in-system performance. The ATF750LVC is a high- performance CMOS (electrically-erasable) complex programmable logic device (CPLD) that utilizes Atmels proven electrically-erasable technology. 1447FPLD11/083. Pin Configurations Pin Name Function CLK Clock IN Logic Inputs I/O Bi-directional Buffers GND Ground VCC 3V to 5.5V Supply 3.1 PLCC 3.2 DIP/SOIC/TSSOP CLK/IN 1 24 VCC IN 2 23 I/O IN 3 22 I/O IN 5 25 I/O IN 4 21 I/O IN 6 24 I/O IN 5 20 I/O IN 7 23 I/O IN 6 19 I/O (1) (1) GND 8 22 GND IN 7 18 I/O IN 9 21 I/O IN 8 17 I/O IN 10 20 I/O IN 9 16 I/O IN 11 19 I/O IN 10 15 I/O IN 11 14 I/O GND 12 13 IN Note: 1. For PLCC, pins 1, 8, 15, and 22 can be left unconnected. For superior performance, connect VCC to pin 1 and GND to pins 8, 15, and 22. Each of the ATF750LVCs 22 logic pins can be used as an input. Ten of these can be used as inputs, outputs or bi-directional I/O pins. Each flip-flop is individually configurable as either D- or T-type. Each flip-flop output is fed back into the array independently. This allows burying of all the sum terms and flip-flops. There are 171 total product terms available. There are two sum terms per output, providing added flexibility. A variable format is used to assign between four to eight product terms per sum term. Much more logic can be replaced by this device than by any other 24-pin PLD. With 20 sum terms and flip-flops, complex state machines are easily implemented with logic to spare. Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flip- flop may also be individually configured to have direct input pin controlled clocking. Each out- put has its own enable product term. One product term provides a common synchronous preset for all flip-flops. Register preload functions are provided to simplify testing. All registers automatically reset upon power-up. 2 ATF750LVC 1447FPLD11/08 IN 12 4 IN IN 13 3 IN GND 14 2 CLK/IN (1) (1) GND 15 1 VCC IN 16 28 VCC I/O 17 27 I/O I/O 18 26 I/O