SAM4C Series Atmel SMART ARM-based Flash MCU DATASHEET Description The Atmel SMART SAM4C microcontrollers are system-on-chip solutions for smart energy applications, built around two high-performance 32-bit ARM Cortex -M4 RISC processors. These devices operate at a maximum speed of 120 MHz and feature up to 2 Mbytes of embedded Flash, up to 304 Kbytes of SRAM and on-chip cache for each core. The dual ARM Cortex-M4 architecture allows for integration of an application layer, communications layers and security functions in a single device, with the ability to extend program and data memory via a 16-bit external bus interface. The peripheral set includes advanced cryptographic engine, anti-tamper, floating point unit (FPU), USB Full-speed Host/Device port, five USARTs, two UARTs, two TWIs, up to seven SPIs, as well as a PWM timer, two 3-channel general-purpose 16-bit timers, calibrated low-power RTC running on the backup domain down to 0.5 A, and a 50 6 segmented LCD controller. The SAM4C series is a scalable platform providing, alongside Atmel s industry leading SAM4 standard microcontrollers, unprecedented cost structure, performance and flexibility to smart meter designers worldwide. Atmel-11102G-ATARM-SAM4C32-SAM4C16-SAM4C8-SAM4C4-Datasheet 24-Oct-16Features Application/Master Core (1) ARM Cortex-M4 running at up to 120 MHz Memory Protection Unit (MPU) DSP Instruction Thumb -2 instruction set Instruction and Data Cache Controller with 2 Kbytes Cache Memory Memories Up to 2 Mbytes of Embedded Flash for Program Code (I-Code bus) and Program Data (D-Code bus) with Built-in ECC (2-bit error detection and 1-bit correction per 128 bits) Up to 256 Kbytes of Embedded SRAM (SRAM0) for Program Data (System bus) 8 Kbytes of ROM with embedded bootloader routines (UART) and In-Application Programming (IAP) routines Coprocessor (provides ability to separate application, communication or metrology functions) (1) ARM Cortex-M4F running at up to 120 MHz IEEE 754 Compliant, Single-precision Floating-Point Unit (FPU) DSP Instruction Thumb-2 instruction set Instruction and Data Cache Controller with 2 Kbytes of Cache Memory Memories Up to 32 Kbytes of Embedded SRAM (SRAM1) for Program Code (I-Code bus) and Program Data (D-Code bus and System bus) Up to 16 Kbytes of Embedded SRAM (SRAM2) for Program Data (System bus) Symmetrical/Asynchronous Dual Core Architecture Interrupt-based Interprocessor Communication Asynchronous Clocking One Interrupt Controller (NVIC) for each core Each Peripheral IRQ routed to each NVIC Input Cryptography High-performance AES 128 to 256 with various modes (GCM, CBC, ECB, CFB, CBC-MAC, CTR) TRNG (up to 38 Mbit/s stream, with tested Diehard and FIPS) Public Key Crypto accelerator and associated ROM library for RSA, ECC, DSA, ECDSA Integrity Check Module (ICM) based on Secure Hash Algorithm (SHA1, SHA224, SHA256), DMA-assisted Safety Up to four physical Anti-tamper Detection I/Os with Time Stamping and Immediate Clear of General Backup Registers Security Bit for Device Protection from JTAG Accesses Shared System Controller Power Supply Embedded core and LCD voltage regulator for single-supply operation Power-on-Reset (POR), Brownout Detector (BOD) and Dual Watchdog for safe operation Ultra-low-power Backup mode (< 0.5 A Typical 25C) 2 SAM4C Series DATASHEET Atmel-11102G-ATARM-SAM4C32-SAM4C16-SAM4C8-SAM4C4-Datasheet 24-Oct-16