SAM4CP16B Atmel SMART Power Line Communications Device DATASHEET Description The SAM4CP series belongs to Atmel SMART energy portfolio. It is based on SAM4C, a high performance 32-bit, dual core ARM Cortex -M4 RISC processor embedding a PRIME PLC Power Line Communication modem. The cores are able to operate at a maximum speed of 120 MHz, featuring 1 Mbyte of embedded Flash, 128 kBytes of SRAM and on-chip cache for each core. SAM4CP unique dual ARM Cortex-M4 architecture supports implementation of signal pro- cessing, application and communications firmware in independent partitions. SAM4CP16B system-on-chip includes a PRIME modem, being PRIME PoweR line Intelligent Metering Evo- lution an open standard technology used for Smart Grid applications, mainly Smart Metering. Atmel PRIME modem implementation includes enhanced PHY layer features such as addi- tional robust modes and frequency band extension. The peripheral set includes advanced cryptographic engine, anti-tamper, floating point unit (FPU), 5x USARTs, 2x UARTs, 2x TWIs, 6 x SPI, as well as 1 PWM timer, 2x three channel general-purpose 16-bit timers an RTC, a 10-bit ADC, and a 46 x 5 Segmented LCD controller. The SAM4CP series is a scalable platform providing, alongside Atmels industry leading SAM4 standard microcontrollers, unprecedented cost structure, performance and flexibility to smart meter designers worldwide. It operates from 1.62V to 3.6V and is available in 176-pin LQFP package. Atmel-43051K-ATPL-SAM4CP16B-Datasheet 22-Sep-161. Features Application/Master Core (CM4P0) (1) ARM Cortex-M4 running at up to 120 MHz Memory Protection Unit (MPU) DSP Instruction Thumb -2 instruction set Instruction and Data Cache Controller with 2 Kbytes Cache Memory Memories 1024 Kbytes of Embedded Flash for Program Code (I-Code bus) and Program Data (D-Code bus) with Built-in ECC (2-bit error detection and 1-bit correction per 128 bits) 128 Kbytes of Embedded SRAM (SRAM0) for Program Data (System bus) 8 Kbytes of ROM with embedded boot loader routines (UART) and In-Application Programming (IAP) routines Co-processor (CM4P1), provides ability to separate application, communication or metrology functions (1) ARM Cortex-M4F running at up to 120 MHz IEEE 754 Compliant, Single-precision Floating-Point Unit (FPU) DSP Instruction Thumb-2 instruction set Instruction and Data Cache Controller with 2 Kbytes of Cache Memory Memories 16 Kbytes of Embedded SRAM (SRAM1) for Program Code (I-Code bus) and Program Data (D- Code bus and System bus) 8 Kbytes of Embedded SRAM (SRAM2) for Program Data (System bus) Symmetrical/Asynchronous Dual Core Architecture Interrupt-based Interprocessor Communication Asynchronous Clocking One Interrupt Controller (NVIC) for each core Each Peripheral IRQ routed to each NVIC Input PRIME PLC Modem Power Line Carrier Modem for 50 Hz and 60 Hz mains 97-carriers OFDM PRIME compliant DBPSK, DQPSK, D8PSK modulation schemes available Additional enhanced modes available: DBPSK Robust and DQPSK Robust Eight selectable channels between 42kHz to 472kHz available. Only one channel can be active at a time Baud rate Selectable: 5.4 to 128.6 kbps Four dedicated buffers for transmission/reception Up to 124.6 dB Vrms injected signal against PRIME load Up to 79.6 dB of dynamic range in PRIME networks Automatic Gain Control and continuous amplitude tracking in signal reception Class D switching power amplifier control Integrated 1.2V LDO regulator to supply analog functions Medium Access Control co-processor features Viterbi soft decoding and PRIME CRC calculation 128-bit AES encryption Channel sensing and collision pre-detection 2 SAM4CP16B DATASHEET Atmel-43051K-ATPL-SAM4CP16B-Datasheet 22-Sep-16