SAM L10/L11 Family
Ultra Low-Power, 32-bit Cortex-M23 MCUs with TrustZone,
Crypto, and Enhanced PTC
Features
Operating Conditions: 1.62V to 3.63V, -40C to +125C, DC to 32 MHz
Core: 32 MHz (2.64 CoreMark/MHz and up to 31 DMIPS) Arm Cortex -M23 with:
Single-cycle hardware multiplier
Hardware divider
Nested Vector Interrupt Controller (NVIC)
Memory Protection Unit (MPU)
Stack Limit Checking
TrustZone for ARMv8-M (optional)
System
Power-on Reset (POR) and programmable Brown-out Detection (BOD)
8-channel Direct Memory Access Controller (DMAC)
8-channel event system for Inter-peripheral Core-independent Operation
CRC-32 generator
Memory
64/32/16 KB Flash
16/8/4 KB SRAM
2 KB Data Flash Write-While-Read (WWR) section for non-volatile data storage
256 bytes TrustRAM with physical protection features
Clock Management
Flexible clock distribution optimized for low power
32.768 kHz crystal oscillator
32.768 kHz ultra low-power internal RC oscillator
0.4 to 32 MHz crystal oscillator
16/12/8/4 MHz low-power internal RC oscillator
Ultra low-power digital Frequency-Locked Loop (DFLLULP)
32-96 MHz fractional digital Phase-Locked Loop (FDPLL96M)
One frequency meter
Low-Power and Power Management
Active, Idle, Standby with partial or full SRAM retention and off sleep modes:
Active mode (< 25 A/MHz)
Idle mode (< 10 A/MHz) with 1.5 s wake-up time
Datasheet DS60001513D-page 1
2019 Microchip Technology Inc. SAM L10/L11 Family
Standby with Full SRAM Retention (0.5 A) with 5.3 s wake-up time
Off mode (< 100 nA)
Static and dynamic power gating architecture
Sleepwalking peripherals
Two performance levels
Embedded Buck/LDO regulator with on-the-fly selection
Security
Up to four tamper pins for static and dynamic intrusion detections
Data Flash
Optimized for secrets storage
Address and Data Scrambling with user-defined key (optional)
Rapid Tamper erase on scrambling key and on one user-defined row
Silent access for side channel attack resistance
TrustRAM
Address and Data scrambling with user-defined key
Chip-level tamper detection on physical RAM to resist microprobing attacks
Rapid Tamper Erase on scrambling key and RAM data
Silent access for side channel attack resistance
Data remanence prevention
Peripherals
One True Random Generator (TRNG)
AES-128, SHA-256, and GCM cryptography accelerators (optional)
Secure pin multiplexing to isolate on dedicated I/O pins a secured communication with
external devices from the non-secure application (optional)
TrustZone for flexible hardware isolation of memories and peripherals (optional)
Up to six regions for the Flash
Up to two regions for the Data Flash
Up to two regions for the SRAM
Individual security attribution for each peripheral, I/O, external interrupt line, and Event
System Channel
Secure Boot with SHA-based authentication (optional)
Up to three debug access levels
Up to three Chip Erase commands to erase part of or the entire embedded memories
Unique 128-bit serial number
SAM L11 Securely Key Provisioned (KPH) (optional)
Key Provisioning using Root of Trust flow
Security Software Framework using Kinibi-M Software Development Kit (SDK)
Advanced Analog and Touch
One 12-bit 1 Msps Analog-to-Digital Converter (ADC) with up to 10 channels
Two Analog Comparators (AC) with window compare function
One 10-bit 350 kSPS Digital-to-Analog Converter (DAC) with external and internal outputs
Three Operational Amplifiers (OPAMP)
DS60001513D-page 2
Datasheet
2019 Microchip Technology Inc.