SAM E70/S70/V70/V71 Family
32-bit ARM Cortex-M7 MCUs with FPU, Audio and
Graphics Interfaces, High-Speed USB, Ethernet, and
Advanced Analog
Features
Core
ARM Cortex -M7 running at up to 300 MHz
16 Kbytes of I-Cache and 16 Kbytes of D-Cache with Error Code Correction (ECC)
Single-precision and double-precision HW Floating Point Unit (FPU)
Memory Protection Unit (MPU) with 16 zones
DSP Instructions, Thumb -2 Instruction Set
Embedded Trace Module (ETM) with instruction trace stream, including Trace Port Interface Unit
(TPIU)
Memories
Up to 2048 Kbytes embedded Flash with unique identifier and user signature for user-defined data
Up to 384 Kbytes embedded Multi-port SRAM
Tightly Coupled Memory (TCM)
16 Kbytes ROM with embedded Bootloader routines (UART0, USB) and IAP routines
16-bit Static Memory Controller (SMC) with support for SRAM, PSRAM, LCD module, NOR and
NAND Flash with on-the-fly scrambling
16-bit SDRAM Controller (SDRAMC) interfacing up to 256 MB and with on-the-fly scrambling
System
Embedded voltage regulator for single-supply operation
Power-on-Reset (POR), Brown-out Detector (BOD) and Dual Watchdog for safe operation
Quartz or ceramic resonator oscillators: 3 to 20 MHz main oscillator with failure detection, 12 MHz
or 16 MHz needed for USB operations. Optional low-power 32.768 kHz for RTC or device clock
RTC with Gregorian calendar mode, waveform generation in low-power modes
RTC counter calibration circuitry compensates for 32.768 kHz crystal frequency variations
32-bit low-power Real-time Timer (RTT)
High-precision Main RC oscillator with 12 MHz default frequency.
32.768 kHz crystal oscillator or Slow RC oscillator as source of low-power mode device clock
(SLCK)
One 500 MHz PLL for system clock, one 480 MHz PLL for USB high-speed operations
Temperature Sensor
One dual-port 24-channel central DMA Controller (XDMAC)
Datasheet DS60001527B-page 1
2018 Microchip Technology Inc. SAM E70/S70/V70/V71 Family
Low-Power Features
Low-power Sleep, Wait and Backup modes, with typical power consumption down to 1.1 A in Backup
mode with RTC, RTT and wakeup logic enabled
Ultra low-power RTC and RTT
1 Kbyte of backup RAM (BRAM) with dedicated regulator
Peripherals
One Ethernet MAC (GMAC) 10/100 Mbps in MII mode and RMII with dedicated DMA. IEEE1588 PTP
frames and 802.3az Energy-efficiency support. Ethernet AVB support with IEEE802.1AS Timestamping
and IEEE802.1Qav credit-based traffic-shaping hardware support.
USB 2.0 Device/Mini Host High-speed (USBHS) at 480 Mbps, 4-Kbyte FIFO, up to 10 bidirectional
endpoints, dedicated DMA
12-bit ITU-R BT. 601/656 Image Sensor Interface (ISI)
Two master Controller Area Networks (MCAN) with Flexible Data Rate (CAN-FD) with SRAM-based
mailboxes, time- and event-triggered transmission
MediaLB device with 3-wire mode, up to 1024 x Fs speed, supporting MOST25 and MOST50
networks
Three USARTs. USART0/1/2 support LIN mode, ISO7816, IrDA , RS-485, SPI, Manchester and
Modem modes; USART1 supports LON mode.
Five 2-wire UARTs with SleepWalking support
2
Three Two-Wire Interfaces (TWIHS) (I C-compatible) with SleepWalking support
Quad I/O Serial Peripheral Interface (QSPI) interfacing up to 256 MB Flash and with eXecute-In-Place
and on-the-fly scrambling
Two Serial Peripheral Interfaces (SPI)
2
One Serial Synchronous Controller (SSC) with I S and TDM support
Two Inter-IC Sound Controllers (I2SC)
One High-speed Multimedia Card Interface (HSMCI) (SDIO/SD Card/e.MMC)
Four Three-Channel 16-bit Timer/Counters (TC) with Capture, Waveform, Compare and PWM modes,
constant on time. Quadrature decoder logic and 2-bit Gray Up/Down Counter for stepper motor
Two 4-channel 16-bit PWMs with complementary outputs, Dead Time Generator and eight fault inputs
per PWM for motor control, two external triggers to manage power factor correction (PFC), DC-DC and
lighting control.
Two Analog Front-End Controllers (AFEC), each supporting up to 12 channels with differential input
mode and programmable gain stage, allowing dual sample-and-hold at up to 1.7 Msps. Offset and gain
error correction feature.
One 2-channel 12-bit 1 Msps-per-channel Digital-to-Analog Controller (DAC) with Differential and Over
Sampling modes
One Analog Comparator Controller (ACC) with flexible input selection, selectable input hysteresis
Cryptography
True Random Number Generator (TRNG)
AES: 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB-197 Specifications
Integrity Check Monitor (ICM). Supports Secure Hash Algorithm SHA1, SHA224 and SHA256.
I/O
Up to 114 I/O lines with external interrupt capability (edge- or level-sensitivity), debouncing, glitch
filtering and On-die Series Resistor Termination
Five Parallel Input/Output Controllers (PIO)
DS60001527B-page 2
Datasheet
2018 Microchip Technology Inc.