ATTINY24-20MU Microchip

Features High Performance, Low Power AVR 8-Bit Microcontroller Advanced RISC Architecture 120 Powerful Instructions Most Single Clock Cycle Execution 32 x 8 General Purpose Working Registers Fully Static Operation Non-Volatile Program and Data Memories 2/4/8K Bytes of In-System Programmable Program Memory Flash Endurance: 10,000 Write/Erase Cycles 8-bit 128/256/512 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles Microcontroller 128/256/512 Bytes of Internal SRAM Data Retention: 20 years at 85C / 100 years at 25C with 2/4/8K Programming Lock for Self-Programming Flash & EEPROM Data Security Peripheral Features Bytes In-System One 8-Bit and One 16-Bit Timer/Counter with Two PWM Channels, Each 10-bit ADC Programmable 8 Single-Ended Channels 12 Differential ADC Channel Pairs with Programmable Gain (1x / 20x) Flash Programmable Watchdog Timer with Separate On-chip Oscillator On-chip Analog Comparator Universal Serial Interface ATtiny24 Special Microcontroller Features debugWIRE On-chip Debug System ATtiny44 In-System Programmable via SPI Port Internal and External Interrupt Sources: Pin Change Interrupt on 12 Pins ATtiny84 Low Power Idle, ADC Noise Reduction, Standby and Power-Down Modes Enhanced Power-on Reset Circuit Programmable Brown-out Detection Circuit Internal Calibrated Oscillator On-chip Temperature Sensor I/O and Packages Available in 20-Pin QFN/MLF & 14-Pin SOIC and PDIP Twelve Programmable I/O Lines Operating Voltage: 1.8 5.5V for ATtiny24V/44V/84V 2.7 5.5V for ATtiny24/44/84 Speed Grade ATtiny24V/44V/84V 0 4 MHz 1.8 5.5V 0 10 MHz 2.7 5.5V ATtiny24/44/84 0 10 MHz 2.7 5.5V 0 20 MHz 4.5 5.5V Industrial Temperature Range: -40C to +85C Low Power Consumption Active Mode (1 MHz System Clock): 300 A 1.8V Power-Down Mode: 0.1 A 1.8V Rev. 8006KAVR10/101. Pin Configurations Figure 1-1. Pinout ATtiny24/44/84 PDIP/SOIC VCC 1 14 GND (PCINT8/XTAL1/CLKI) PB0 2 13 PA0 (ADC0/AREF/PCINT0) (PCINT9/XTAL2) PB1 3 12 PA1 (ADC1/AIN0/PCINT1) (PCINT11/RESET/dW) PB3 4 11 PA2 (ADC2/AIN1/PCINT2) (PCINT10/INT0/OC0A/CKOUT) PB2 5 10 PA3 (ADC3/T0/PCINT3) (PCINT7/ICP/OC0B/ADC7) PA7 6 9 PA4 (ADC4/USCK/SCL/T1/PCINT4) (PCINT6/OC1A/SDA/MOSI/DI/ADC6) PA6 7 8 PA5 (ADC5/DO/MISO/OC1B/PCINT5) QFN/MLF Pin 16: PA6 (PCINT6/OC1A/SDA/MOSI/DI/ADC6) Pin 20: PA5 (ADC5/DO/MISO/OC1B/PCINT5) (ADC4/USCK/SCL/T1/PCINT4) PA4 1 15 PA7 (PCINT7/ICP/OC0B/ADC7) (ADC3/T0/PCINT3) PA3 2 14 PB2 (PCINT10/INT0/OC0A/CKOUT) (ADC2/AIN1/PCINT2) PA2 3 13 PB3 (PCINT11/RESET/dW) (ADC1/AIN0/PCINT1) PA1 4 12 PB1 (PCINT9/XTAL2) (ADC0/AREF/PCINT0) PA0 5 11 PB0 (PCINT8/XTAL1/CLKI) NOTE Bottom pad should be soldered to ground. DNC: Do Not Connect 1.1 Pin Descriptions 1.1.1 VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB3:PB0) Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of RESET pin, program (0) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. 2 ATtiny24/44/84 8006KAVR10/10 DNC 6 20 PA5 DNC 7 19 DNC GND 8 18 DNC VCC 9 17 DNC DNC 10 16 PA6