AY0438 32-Segment CMOS LCD Driver FEATURES PIN CONFIGURATION 40-Lead Dual In-line Drives up to 32 LCD segments of arbitrary cong- uration VDD 1 40 CLOCK CMOS process for: wide supply voltage range, LOAD 2 39 SEG 1 low- power operation, high-noise immunity, wide SEG 32 3 38 SEG 2 SEG 31 4 37 SEG 3 temperature range SEG 30 5 36 VSS CMOS and TTL-compatible inputs SEG 29 6 35 DATA OUT Electrostatic discharge protection on all pins SEG 28 7 34 DATA IN SEG 27 8 33 SEG 4 Cascadable SEG 26 9 32 SEG 5 On-chip oscillator SEG 25 10 31 LCDF Requires only three control lines SEG 24 11 30 BP SEG 23 12 29 SEG 6 APPLICATIONS SEG 22 13 28 SEG 7 SEG 21 14 27 SEG 8 Industrial displays SEG 20 15 26 SEG 9 SEG 19 16 25 SEG 10 Consumer product displays SEG 18 17 24 SEG 11 Telecom product displays SEG 17 18 23 SEG 12 Automotive dashboard displays SEG 16 19 22 SEG 13 SEG 15 20 21 SEG 14 DESCRIPTION The AY0438 is a CMOS integrated device that drives a liquid crystal display, usually under microprocessor control. The part acts as a smart peripheral that drives up to 32 LCD segments. It needs only three control lines due to its serial input construction. It latches the 44 PLCC data to be displayed and relieves the microprocessor from the task of generating the required waveforms. The AY0438 can drive any standard or custom parallel drive LCD display, whether it be eld effect or dynamic scattering 7-, 9-, 14- or 16-segment characters deci- mals leading + or - or special symbols. Several AY0438 devices can be cascaded. The AC frequency SEG 29 NC 7 39 of the LCD waveforms can either be supplied by the SEG 28 8 38 DATA OUT DATA IN SEG 27 9 37 user or generated by attaching a capacitor to the LCD SEG 26 10 36 SEG 4 input, which controls the frequency of an internal oscil- SEG 25 SEG 5 11 35 SEG 24 12 34 LCDF lator. AY0438 SEG 23 BP 13 33 SEG 22 14 32 SEG 6 The AY0438 is available in 40-lead dual in-line plastic SEG 21 SEG 7 15 31 and 44-lead PLCC packages. Unpackaged dice are SEG 20 16 30 SEG 8 SEG 19 17 29 NC also available. 1995 Microchip Technology Inc. DS70010I-page 1 SEG 18 18 6 NC SEG 17 5 SEG 30 19 SEG 16 4 20 SEG 31 SEG 15 21 3 SEG 32 SEG 14 2 LOAD 22 AY0438 SEG 13 23 1 VDD SEG 12 44 24 CLOCK SEG 11 25 43 SEG 1 SEG 10 42 SEG 2 26 SEG 9 41 27 SEG 3 NC 40 VSS 28 AY0438 FIGURE 1: PIN DESCRIPTIONS Pin (PDIP Only) Name Direction Description DD 1V - Supply voltage 2 Load Input Latch data from registers 3-29, 32, 33, 37-39 Seg 1-32 Output Direct drive outputs 30 BP Output Backplane drive output 31 LCDF Input Backplane drive input 34 Data In Input Data input to shift register 35 Data Out Output Data output from shift register SS 36 V Ground Ground 40 Clock Input System clock input FIGURE 2: BLOCK DIAGRAM FIGURE 3: BACKPLANE AND SEGMENT OUTPUT Data in Data out 32-bit Static Shift Register Clock SEG On Load 32 Latches 32 Segment Drivers Backplane 32 Outputs LCD AC Backplane LCDF Generator output SEG Off FIGURE 4: TIMING DIAGRAM 1/f CLOCK 1 31 32 START Data in SEG 32 SEG 2 SEG 1 tDS tDH Data out tPD Load tPW enabled or visible, i.e. the output at Segment Output is 1.0 OPERATION: 180 out-of-phase with the Backplane output (Figure 3). 1.1 Data In and Clock The shift register shifts and outputs on the falling edge 1.2 Load of the clock. Every clock falling edge does a logical left A logic 1 at the Load input (Figure 2) causes the paral- shift. As an example, if 32 clock pulses are supplied as lel load of the data in the shift register into the latches in Figure 4, then the data input at the rst clock will out- that control the segment drivers. If the Load signal is put at SEG 32, and the last data input ( 32) will output tied high, then the latches become transparent and the at SEG 1 when a LOAD signal is enabled (Figure 2). It segment drivers are always connected to the shift reg- is recommended that a complete 32 bit transfer be isters. done every time the outputs are updated. A logic 1 at the Data In causes the corresponding segment to be DS70010I-page 2 1995 Microchip Technology Inc.